Abstract: A touch input device includes a circuit board, a plurality of illuminant elements disposed on the circuit board, a spacer disposed over the circuit board, a plurality of light guide plates, a shielding sheet, and a top plate. The circuit board has a board edge and an upper surface having a plurality of sensing regions. The spacer has a light-leaking edge and a plurality of accommodation holes for accommodating the illuminant elements and the light guide plates. The shielding sheet includes a main section covering the spacer, a first extension section covering the light-leaking edge and the board edge, and a second extension section combined with the circuit board. The main section has a plurality of light permeable regions respectively corresponding to the light guide plates. The top plate is disposed on the main section and has a plurality of light-exit regions.

Abstract: A semiconductor structure according to the present disclosure includes a circuit region disposed over a substrate and a seal ring region disposed over the substrate and completely surrounding the circuit region. The circuit region includes first fins, second fins, n-type epitaxial structures over the first fins, and p-type epitaxial structures over the second fins. The seal ring region includes fin rings extending completely around the circuit region, epitaxial rings disposed over and extending parallel to the fin rings. All of the epitaxial rings over all of the fin rings in the seal ring region are p-type epitaxial rings.

Abstract: Some embodiments relate to a ferroelectric random access memory (FeRAM) device. The FeRAM device includes a bottom electrode structure and a top electrode overlying the ferroelectric structure. The top electrode has a first width as measured between outermost sidewalls of the top electrode. A ferroelectric structure separates the bottom electrode structure from the top electrode. The ferroelectric structure has a second width as measured between outermost sidewalls of the ferroelectric structure. The second width is greater than the first width such that the ferroelectric structure includes a ledge that reflects a difference between the first width and the second width. A dielectric sidewall spacer structure is disposed on the ledge and covers the outermost sidewalls of the top electrode.

Abstract: A photographing optical lens system includes seven lens elements which are, in order from an object side to an image side: a first lens element, a second lens element, a third lens element, a fourth lens element, a fifth lens element, a sixth lens element and a seventh lens element. Each of the seven lens elements has an object-side surface facing toward the object side and an image-side surface facing toward the image side. The object-side surface of the first lens element is convex in a paraxial region thereof. The seventh lens element has negative refractive power. The object-side surface of the seventh lens element is concave in a paraxial region thereof. At least one of all lens surfaces of the seven lens elements is aspheric and has at least one inflection point.

Abstract: A semiconductor structure includes a circuit substrate, a semiconductor die, and a cover. The semiconductor die is disposed on the circuit substrate. The cover is disposed over the semiconductor die and over the circuit substrate. The cover comprises a lid portion and a support portion. The structure includes a first adhesive bonding the support portion to the circuit substrate and a second adhesive bonding the support portion and the lid portion.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure.

Abstract: A transmission gate structure includes first and second PMOS transistors positioned in a first active area, first and second NMOS transistors positioned in a second active area parallel to the first active area, and four metal segments parallel to the active areas. A first metal segment overlies the first active area, a fourth metal segment overlies the second active area, and second and third metal segments are a total of two metal segments positioned between the first and fourth metal segments. A first conductive path connects gates of the first PMOS and NMOS transistors, a second conductive path connects gates of the second PMOS and NMOS transistors, a third conductive path connects a source/drain (S/D) terminal of each of the first and second PMOS transistors and first and second NMOS transistors and includes a first conductive segment extending across at least three of the four metal segments.

Abstract: Some embodiments of the present disclosure are directed to systems, computer-readable media, and computer-implemented methods for neural network training. Some embodiments are directed to determining an attack order schedule for the data sample that includes a plurality of adversarial perturbation attacks associated with the data sample, and performing a composite adversarial attack process against the data set using the determined attack order schedule to generate a perturbed data sample for the data sample. Other embodiments may be disclosed or claimed.

Abstract: Techniques according to the present disclosure may include receiving, at a computer, a command for performing an action on a first image layer of a first container repository. A second container repository is determined which has a dependency on the first container repository, based on a dependency graph storing dependencies of a plurality of container repositories. The action is performed on the first image layer of the first container repository and a corresponding action on a second image layer of the second container repository based on the command.

Abstract: An integrated circuit is provided which includes a first complementary field-effect transistor and a second complementary field-effect transistor. The first complementary field-effect transistor includes at least two first transistors respectively located on a first layer and a second layer. The second complementary field-effect transistor is disposed adjacent to the first complementary field-effect transistor. The second complementary field-effect transistor includes at least two second transistors respectively located on the first layer and the second layer. Type of one of the at least two first transistors located on the first layer is different from type of one of the at least two second transistors located on the first layer.

Abstract: A wafer with micro integrated circuits includes a transparent substrate and a plurality of micro components. The micro components are each attached to the transparent substrate by a plurality of transparent adhesive layers. Each of the micro components includes a bonding pad in direct contact with the transparent adhesive layer and an etching stop layer located on the side of the micro components opposite from the bonding pad.

Abstract: A semiconductor device includes a supporting structure, a die stack, and a redistribution circuit structure. The die stack is disposed over the supporting structure and includes a first semiconductor die comprising a substrate and a second semiconductor die, where the first semiconductor die is between the second semiconductor die and the supporting structure, and a material of the supporting structure is different from a material of the substrate of the first semiconductor die. The redistribution circuit structure is disposed over the die stack and electrically coupled to the first semiconductor die and the second semiconductor die.

Abstract: According to one embodiment, a magnetic disk device includes a first MA amplifier that drives a first micro actuator that positions a corresponding magnetic head, a second micro actuator that positions a corresponding magnetic head, a second MA amplifier that drives the second micro actuator, and a controller that, when performing switching from an MA amplifier of a switching source in an on state to an MA amplifier of a switching destination in an off state, starts up the MA amplifier of the switching destination while maintaining the MA amplifier of the switching source in the on state, and performs the switching from the MA amplifier of the switching source to the MA amplifier of the switching destination after a predetermined time elapses.

Abstract: A controllable aperture stop includes a light pass portion, a fixed portion, a driving part and rollable elements. The light pass portion includes movable blades together surrounding a light pass aperture. The fixed portion has shaft structures corresponding to the movable blades. The driving part includes a rotatable element, a magnet and a coil. The rotatable element is for driving the movable blades to rotate relative to the shaft structures to adjust the size of the light pass aperture. The magnet is disposed on the rotatable element. The coil corresponds to the magnet. The magnet and the coil are to drive the rotatable element to rotate around the light pass aperture. The rollable elements are disposed between the fixed portion and the rotatable element and arranged around the light pass aperture, so the rotatable element is rotatable relative to the fixed portion.

Abstract: A semiconductor device includes a gate isolation structure on a shallow trench isolation (STI), a first epitaxial layer on one side of the gate isolation structure, a second epitaxial layer on another side of the gate isolation structure, first fin-shaped structures directly under the first epitaxial layer, and second fin-shaped structures directly under the second epitaxial layer, in which the STI surrounds the first fin-shaped structures and the second fin-shaped structures.

Abstract: The present invention is related to a method and pharmaceutical composition for treating a cartilage damage in a subject (including a human or an animal), particularly osteoarthritis (OA), using extracellular vesicles (EVs) with SOX9 gene, called as “EV-SOX9”. The EV-SOX9 is obtained by encapsulating the SOX9 mRNA or the mRNA of its upstream and downstream gene in EVs, naïve EVs with high expression level of SOX9 mRNA or its upstream and downstream gene from different cell sources, or MSC-derived EV-SOX9, which is obtained by transferring the SOX9 gene or its upstream and downstream gene into a multipotent cell and collecting EVs.

Abstract: The present disclosure provides an image capturing optical system comprising: a positive first lens element having a convex object-side surface; a negative second lens element having a concave object-side surface; a third lens element; a fourth lens element having a convex object-side surface and a concave image-side surface, the object-side surface and the image-side surface thereof being aspheric; a fifth lens element having a concave image-side surface concave, both of the object-side surface and the image-side surface being aspheric, at least one of the object-side surface and the image-side surface having at least one convex shape in an off-axis region thereof.

Abstract: The present disclosure provides a method and an apparatus for arranging electrical components within a semiconductor device, and a non-transitory computer-readable medium. The method includes (a) placing a plurality of cells in a first layout; (b) generating a second layout by performing a first set of calculations on the first layout such that a total wire length of the second layout is less than that of the first layout; (c) generating a third layout by performing a second set of calculations on the second layout such that cell congestions in the second layout is eliminated from the third layout; (d) generating a fourth layout by performing a third set of calculations on the third layout such that the total wire length of the fourth layout is less than that of the third layout; and (e) iterating the operations (c) and (d) until a target layout conforms to a convergence criterion.

Abstract: An imaging optical lens assembly includes five optical elements with refractive power. The five optical elements, in order from an object side to an image side along an optical path, are a first optical element, a second optical element, a third optical element, a fourth optical element, and a fifth optical element. The first optical element has an object-side surface being concave in a paraxial region thereof. The third optical element has negative refractive power.

Abstract: A method includes etching a dielectric layer to form an opening. A first conductive feature underlying the dielectric layer is exposed to the opening. A sacrificial spacer layer is deposited to extend into the opening. The sacrificial spacer layer is patterned. A bottom portion of the sacrificial spacer layer at a bottom of the opening is removed to reveal the first conductive feature, and a vertical portion of the sacrificial spacer layer in the opening and on sidewalls of the dielectric layer is left to form a ring. A second conductive feature is formed in the opening. The second conductive feature is encircled by the ring, and is over and electrically coupled to the first conductive feature. At least a portion of the ring is removed to form an air spacer.