Abstract: A Hamming weight encoder includes an input that receives user data including P symbols and a Hamming weight module that determines a Hamming weight of N of said P symbols. N and P are integers greater than one and N is less than or equal to P. The Hamming weight encoder also includes a comparing module that compares the Hamming weight to a Hamming weight threshold and an inverting module that selectively bitwise inverts bits in said N symbols based on said comparison.

Abstract: A method comprising receiving a pulse generated in response to a transition of a head over a predetermined pattern on a storage medium, measuring a first amplitude of a power spectrum of the pulse at a first predetermined frequency and a second amplitude of the power spectrum of the pulse at respective second predetermined frequencies, and calculating a distance between the head and the storage medium based on a function of the first and second amplitudes.

Abstract: A sync mark detector identifies a sync mark in an incoming bitstream of a communications channel. A bit comparing circuit compares the sync mark bit-by-bit to the incoming bitstream if channel irregularities do not exist. A symbol comparing circuit compares the sync mark symbol-by-symbol to the incoming bitstream if channel irregularities do exist. The bit comparing circuit implements a bit level matching rule. The symbol comparing circuit implements a symbol level matching rule. The bit comparing circuit generates a sync mark found state when the bit level matching rule is satisfied. The symbol comparing circuit generates a sync mark found state when the symbol level matching rule is satisfied. Post coding such as NRZ, INRZI, or NRZI can be used.

Abstract: A phase locked loop has an average zero phase start circuit to detect and correct for the average phase difference between a data signal and a VCO clock signal over a short interval at the beginning of phase-lock acquisition. The average zero phase start circuit has a data comparator to split the data stream into odd and even portions; odd and even pulse position detectors to detect the phase difference between pulses of the odd and even data signals and corresponding pulses of the VCO clock; and a ramp generator to generate a voltage corresponding to the sum of the detected phase differences. The ramp generator employs a capacitor and switched current sources that discharge the capacitor at a fixed rate to generate the voltage. After 4 phase difference measurements are taken, the VCO is stopped, and another current source discharges the capacitor at 4 times the fixed rate.