Abstract: A heat-assisted magnetic recording system may include, but is not limited to: at least one magnetic recording read/write head; at least one laser diode configured to illuminate at least a portion of at least one magnetic recording medium; at least one laser power level sensor configured to detect a power level of the at least one laser diode; and a controller configured to modify one or more power level settings associated with the at least one laser diode in response to one or more output signals of the at least one laser power level sensor.

Abstract: A heat-assisted magnetic recording system may include, but is not limited to: at least one magnetic recording read/write head; at least one laser diode configured to illuminate at least a portion of at least one magnetic recording medium; at least one laser power level sensor configured to detect a power level of the at least one laser diode; and a controller configured to modify one or more power level settings associated with the at least one laser diode in response to one or more output signals of the at least one laser power level sensor.

Abstract: A phase-lock loop (PLL) circuit can be locked on to a synthesizer frequency without decreasing the available range of the frequency differences which the PLL circuit can accommodate during a data receive mode. An analog-to-digital conveyer (ADC) receives an analog input signal and responds to a periodic clock signal by providing a corresponding digital output signal. A phase comparator is coupled to receive the ADC digital output signal and to provide a phase error signal which is representative of a phase error in the digital output signal. A filter accumulates the value of the phase error signal into a filter first register to generate a primary frequency error value. The filter further includes a filter second register for holding a secondary frequency error value (e.g., a value which corrects for an offset between a synthesizer frequency and the PLL free-running frequency).

Abstract: A receiver circuit relies on sample data techniques to filter input data signals having a frequency less than a preselected maximum and greater than a preselected minimum. The circuit also rejects a single sine wave cycle. If an input pulse greater than a preselected maximum termination pulse width is encountered during data reception, then reception activity is terminated.

Abstract: A receiver squelch circuit has a programmable DC threshold level. The squelch circuit includes input circuitry that responds to an incoming signal by generating a decision signal when the DC voltage level of the incoming signal crosses a predetermined threshold level. A programmable control network selectively varies the predetermined threshold level.