Abstract: A high-speed magnitude comparator circuit (30) receives two n-bit operands and provides first and second signals for each bit position. The first signal is a logical OR of a complement of a corresponding bit from the first operand and a corresponding bit from the second operand; the second signal is a logical AND of a complement of the corresponding bit from the first operand and the corresponding bit from the second operand. The second signal corresponding to the least-significant bit position is formed differently, as the logical OR of a complement of the least-significant bit of the first operand and the least-significant bit of the second operand. These signals are then provided to pullup (34) and pulldown (35) columns of transistors to determine the results of the comparison in parallel. Thus, the operands need only propagate through three logic levels to provide the result.