Patents by Inventor Tobias Brown
Tobias Brown has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20250133822Abstract: Integrated circuitry comprising a ribbon or wire (RoW) transistor stack within which the transistors have different threshold voltages (Vt). In some examples, a gate electrode of the transistor stack may include only one workfunction metal. A metal oxide may be deposited around one or more channels of the transistor stack as a solid-state source of a metal oxide species that will diffuse toward the channel region(s). As diffused, the metal oxide may remain (e.g., as a silicate, or hafnate) in close proximity to the channel region, thereby altering the dipole properties of the gate insulator material. Different channels of a transistor stack may be exposed to differing amounts or types of the metal oxide species to provide a range of Vt within the stack. After diffusion, the metal oxide may be stripped as sacrificial, or retained.Type: ApplicationFiled: December 24, 2024Publication date: April 24, 2025Applicant: Intel CorporationInventors: Nicole Thomas, Eric Mattson, Sudarat Lee, Scott B. Clendenning, Tobias Brown-Heft, I-Cheng Tung, Thoe Michaelos, Gilbert Dewey, Charles Kuo, Matthew Metz, Marko Radosavljevic, Charles Mokhtarzadeh
-
Patent number: 12183739Abstract: Integrated circuitry comprising a ribbon or wire (RoW) transistor stack within which the transistors have different threshold voltages (Vt). In some examples, a gate electrode of the transistor stack may include only one workfunction metal. A metal oxide may be deposited around one or more channels of the transistor stack as a solid-state source of a metal oxide species that will diffuse toward the channel region(s). As diffused, the metal oxide may remain (e.g., as a silicate, or hafnate) in close proximity to the channel region, thereby altering the dipole properties of the gate insulator material. Different channels of a transistor stack may be exposed to differing amounts or types of the metal oxide species to provide a range of Vt within the stack. After diffusion, the metal oxide may be stripped as sacrificial, or retained.Type: GrantFiled: December 18, 2020Date of Patent: December 31, 2024Assignee: Intel CorporationInventors: Nicole Thomas, Eric Mattson, Sudarat Lee, Scott B. Clendenning, Tobias Brown-Heft, I-Cheng Tung, Thoe Michaelos, Gilbert Dewey, Charles Kuo, Matthew Metz, Marko Radosavljevic, Charles Mokhtarzadeh
-
Publication number: 20240373644Abstract: An integrated circuit capacitor structure, includes a first electrode includes a cylindrical column, a ferroelectric layer around an exterior sidewall of the cylindrical column and a plurality of outer electrodes. The plurality of outer electrodes include a first outer electrode laterally adjacent to a first portion of an exterior of the ferroelectric layer and a second outer electrode laterally adjacent to a second portion of the exterior of the ferroelectric layer, wherein the second outer electrode is above the first outer electrode.Type: ApplicationFiled: July 19, 2024Publication date: November 7, 2024Applicant: Intel CorporationInventors: Nazila Haratipour, Sou-Chi Chang, Shriram Shivaraman, I-Cheng Tung, Tobias Brown-Heft, Devin R. Merrill, Che-Yun Lin, Seung Hoon Sung, Jack Kavalieros, Uygar Avci, Matthew V. Metz
-
Patent number: 12080781Abstract: Thin film transistors fabricated using a spacer as a fin are described. In an example, a method of forming a fin transistor structure includes patterning a plurality of backbone pillars on a semiconductor substrate. The method may then include conformally depositing a spacer layer over the plurality of backbone pillars and the semiconductor substrate. A spacer etch of the spacer layer is then performed to leave a sidewall of the spacer layer on a backbone pillar to form a fin of the fin transistor structure. Other embodiments may be described and claimed.Type: GrantFiled: December 21, 2020Date of Patent: September 3, 2024Assignee: Intel CorporationInventors: Noriyuki Sato, Sarah Atanasov, Abhishek A. Sharma, Bernhard Sell, Chieh-Jen Ku, Elliot N. Tan, Hui Jae Yoo, Travis W. Lajoie, Van H. Le, Pei-Hua Wang, Jason Peck, Tobias Brown-Heft
-
Patent number: 12048165Abstract: An integrated circuit capacitor structure, includes a first electrode includes a cylindrical column, a ferroelectric layer around an exterior sidewall of the cylindrical column and a plurality of outer electrodes. The plurality of outer electrodes include a first outer electrode laterally adjacent to a first portion of an exterior of the ferroelectric layer and a second outer electrode laterally adjacent to a second portion of the exterior of the ferroelectric layer, wherein the second outer electrode is above the first outer electrode.Type: GrantFiled: June 26, 2020Date of Patent: July 23, 2024Assignee: Intel CorporationInventors: Nazila Haratipour, Sou-Chi Chang, Shriram Shivaraman, I-Cheng Tung, Tobias Brown-Heft, Devin R. Merrill, Che-Yun Lin, Seung Hoon Sung, Jack Kavalieros, Uygar Avci, Matthew V. Metz
-
Publication number: 20220199620Abstract: Integrated circuitry comprising a ribbon or wire (RoW) transistor stack within which the transistors have different threshold voltages (Vt). In some examples, a gate electrode of the transistor stack may include only one workfunction metal. A metal oxide may be deposited around one or more channels of the transistor stack as a solid-state source of a metal oxide species that will diffuse toward the channel region(s). As diffused, the metal oxide may remain (e.g., as a silicate, or hafnate) in close proximity to the channel region, thereby altering the dipole properties of the gate insulator material. Different channels of a transistor stack may be exposed to differing amounts or types of the metal oxide species to provide a range of Vt within the stack. After diffusion, the metal oxide may be stripped as sacrificial, or retained.Type: ApplicationFiled: December 18, 2020Publication date: June 23, 2022Applicant: Intel CorporationInventors: Nicole Thomas, Eric Mattson, Sudarat Lee, Scott B. Clendenning, Tobias Brown-Heft, I-Cheng Tung, Thoe Michaelos, Gilbert Dewey, Charles Kuo, Matthew Metz, Marko Radosavljevic, Charles Mokhtarzadeh
-
Publication number: 20220199807Abstract: Thin film transistors fabricated using a spacer as a fin are described. In an example, a method of forming a fin transistor structure includes patterning a plurality of backbone pillars on a semiconductor substrate. The method may then include conformally depositing a spacer layer over the plurality of backbone pillars and the semiconductor substrate. A spacer etch of the spacer layer is then performed to leave a sidewall of the spacer layer on a backbone pillar to form a fin of the fin transistor structure.Type: ApplicationFiled: December 21, 2020Publication date: June 23, 2022Inventors: Noriyuki SATO, Sarah ATANASOV, Abhishek A. Sharma, Bernhard SELL, Chieh-Jen KU, Elliot N. TAN, Hui Jae YOO, Travis W. LAJOIE, Van H. LE, Pei-Hua WANG, Jason PECK, Tobias BROWN-HEFT
-
GATE DIELECTRICS FOR COMPLEMENTARY METAL OXIDE SEMICONDUCTORS TRANSISTORS AND METHODS OF FABRICATION
Publication number: 20220199619Abstract: A complementary metal oxide semiconductor (CMOS) transistor includes a first transistor with a first gate dielectric layer above a first channel, where the first gate dielectric layer includes Hf1-xZxO2, where 0.33<x<0.5. The first transistor further includes a first gate electrode on the first gate dielectric layer and a first source region and a first drain region on opposite sides of the first gate electrode. The CMOS transistor further includes a second transistor adjacent to the first transistor. The second transistor includes a second gate dielectric layer above a second channel, where the second gate dielectric layer includes Hf1-xZxO2, where 0.5<x<0.99, a second gate electrode on the second gate dielectric layer and a second source region and a second drain region on opposite sides of the second gate electrode.Type: ApplicationFiled: December 23, 2020Publication date: June 23, 2022Applicant: Intel CorporationInventors: Ashish Verma Penumatcha, Seung Hoon Sung, Jack Kavalieros, Uygar Avci, Tristan Tronic, Shriram Shivaraman, Devin Merrill, Tobias Brown-Heft, Kirby Maxey, Matthew Metz, Ian Young -
Publication number: 20210408018Abstract: An integrated circuit capacitor structure, includes a first electrode includes a cylindrical column, a ferroelectric layer around an exterior sidewall of the cylindrical column and a plurality of outer electrodes. The plurality of outer electrodes include a first outer electrode laterally adjacent to a first portion of an exterior of the ferroelectric layer and a second outer electrode laterally adjacent to a second portion of the exterior of the ferroelectric layer, wherein the second outer electrode is above the first outer electrode.Type: ApplicationFiled: June 26, 2020Publication date: December 30, 2021Applicant: Intel CorporationInventors: Nazila Haratipour, Sou-Chi Chang, Shriram Shivaraman, I-Cheng Tung, Tobias Brown-Heft, Devin R. Merrill, Che-Yun Lin, Seung Hoon Sung, Jack Kavalieros, Uygar Avci, Matthew V. Metz
-
Patent number: 9802101Abstract: An apparatus for counting attempts in a sporting game includes a housing with a display for displaying at least a running count of attempts; wrist band means having opposing first and second sides, being connected at the first side with the housing, and being sized and configured to encircle a person's wrist proximal the person's palm; an input contact member mounted at the second side of the wristband means for movement upon contact with the person's palm; an attempt input assembly operably connected with the input contact member to transmit an electrical signal upon detecting movement of the input contact member by the palm; and electronic processing and power elements for receiving input from the attempt input assembly and causing the display to display information related to the movement registered by the input contact member.Type: GrantFiled: May 19, 2015Date of Patent: October 31, 2017Inventor: Tobias Brown
-
Patent number: 7641517Abstract: A lamp base has a projection that carries lamp contacts and has an outer surface formed with retaining formations arrayed with irregular spacing. A socket forms a recess into which the projection can be inserted with play and apertures provided with contacts engageable with the lamp contacts. Retaining formations in the socket fit with the lamp-base retaining formations in only one defined angular alignment of the lamp base and the socket. The projection has a central plug projecting toward the socket and forming a lamp key coded for a predetermined lamp wattage. The socket has a hole corresponding to the plug and itself forming a socket key coded for the maximally admissible lamp wattage for the socket. The lamp base only fits into the socket when the lamp wattage indicated by the lamp key does not exceed the maximally admissible lamp wattage defined by the socket key.Type: GrantFiled: February 12, 2008Date of Patent: January 5, 2010Assignees: BJB GmbH & Co. KG, Osram Sylvania Inc.Inventors: Karl-Wilhelm Vogt, Tobias Brown, Markus Pieper, Albert M. Cavallaro, Roger B. Hunt, Jr., Dennis S. Holt
-
Publication number: 20090203260Abstract: A device for holding a compact fluorescent lamp in a light fixture with a socket 10 and a lamp base is shown and described. The bayonet-type fixing of the lamp base in a socket 10 is effected by means of a plug-and-rotate motion. In order to give manufacturers of light fixtures the possibility of manufacturing light fixtures for lamps with a predetermined or maximally admissible lamp wattage, the invention proposes a key system with seven key pairs. Each key pair comprises a lamp key and a socket key and characterizes a predetermined lamp wattage. Concretely speaking, the socket key is a lug arranged in a hole and the lamp key is a plug corresponding to the socket hole with a outwardly open cutout. In addition, a key system for making predetermined lamp types recognizable is described.Type: ApplicationFiled: February 12, 2008Publication date: August 13, 2009Inventors: Karl-Wilhelm Vogt, Tobias Brown, Markus Pieper, Albert M. Cavallaro, Roger B. Hunt, JR., Dennis S. Holt
-
Patent number: 5014353Abstract: A face protecting device comprising a generally concave shield having an inwardly projecting peripheral border portion and provided with an observation opening therein, said shield being further provided with two spaced angularly disposed hand grips in the lower portion thereof.Type: GrantFiled: December 14, 1989Date of Patent: May 14, 1991Assignee: Sellstrom Manufacturing CompanyInventors: Tobias Brown, Burton L. Siegal
-
Patent number: D295329Type: GrantFiled: August 14, 1985Date of Patent: April 19, 1988Assignee: Alkco Manufacturing CompanyInventors: Scott Roos, Tobias Brown
-
Patent number: D305694Type: GrantFiled: July 28, 1986Date of Patent: January 23, 1990Assignee: Alkco Manufacturing CompanyInventor: Tobias Brown
-
Patent number: D312886Type: GrantFiled: April 14, 1988Date of Patent: December 11, 1990Assignee: Alkco Manufacturing CompanyInventor: Tobias Brown
-
Patent number: D313866Type: GrantFiled: April 14, 1988Date of Patent: January 15, 1991Assignee: Alkco Manufacturing CompanyInventor: Tobias Brown
-
Patent number: D321957Type: GrantFiled: December 14, 1989Date of Patent: November 26, 1991Assignee: Sellstrom Manufacturing CompanyInventors: Tobias Brown, Burton L. Siegal