Abstract: An apparatus for generating an oscillation signal is provided. The apparatus includes an input configured to receive a first reference oscillation signal, and a phase detector circuit configured to determine a phase drift of the first reference oscillation signal with respect to a second reference oscillation signal. Further, the apparatus includes a phase shifter circuit configured to generate the oscillation signal based on the first reference oscillation signal and a control signal. The control signal is based on the phase drift and a frequency control signal comprising control data for the phase shifter circuit for adjusting a frequency of the oscillation signal to a desired frequency.

Abstract: A digital phase-locked loop has a digitally controlled oscillator with a first coarse tuning field for coarse tuning of the oscillator frequency, a second coarse tuning field for tuning of the oscillator frequency at finer intervals than the first coarse tuning field, and a fine tuning field for tuning the oscillator to an output frequency at finer intervals than the second coarse tuning field. The second coarse tuning field provides open loop tuning and is linear and connected parallel to the first coarse tuning field. The second coarse tuning field provides wide field temperature compensation and frequency error determination at start up based on an interpolated frequency value obtained prior to start up. Faster settling is provided with less complex algorithms.

Abstract: An apparatus for generating an oscillation signal is provided. The apparatus includes an input configured to receive a first reference oscillation signal, and a phase detector circuit configured to determine a phase drift of the first reference oscillation signal with respect to a second reference oscillation signal. Further, the apparatus includes a phase shifter circuit configured to generate the oscillation signal based on the first reference oscillation signal and a control signal. The control signal is based on the phase drift and a frequency control signal comprising control data for the phase shifter circuit for adjusting a frequency of the oscillation signal to a desired frequency.

Abstract: In a modulation correction method, an adjusted amplitude is determined based on an amplitude between adjacent zero crossings of a modulated signal, the adjacent zero crossings are shifted to determine shifted zero crossings, and the modulated signal is adapted based on the adjusted amplitude and the shifted zero crossings to generate a corrected modulated signal corresponding to the modulated signal.

Abstract: A digital phase-locked loop has a digitally controlled oscillator with a first coarse tuning field for coarse tuning of the oscillator frequency, a second coarse tuning field for tuning of the oscillator frequency at finer intervals than the first coarse tuning field, and a fine tuning field for tuning the oscillator to an output frequency at finer intervals than the second coarse tuning field. The second coarse tuning field provides open loop tuning and is linear and connected parallel to the first coarse tuning field. The second coarse tuning field provides wide field temperature compensation and frequency error determination at start up based on an interpolated frequency value obtained prior to start up. Faster settling is provided with less complex algorithms.

Abstract: In a modulation correction method, an adjusted amplitude is determined based on an amplitude between adjacent zero crossings of a modulated signal, the adjacent zero crossings are shifted to determine shifted zero crossings, and the modulated signal is adapted based on the adjusted amplitude and the shifted zero crossings to generate a corrected modulated signal corresponding to the modulated signal.

Abstract: Techniques are disclosed to provide a data dependent delay for a multi-phase transmitter architectures. These techniques include identifying a current segment occupied by a symbol associated with in-phase (I) and quadrature phase (Q) data within a data constellation based upon the number of phases used. Once the segment is identified, vector components are calculated as a function of the segment used to re-map the symbol within the constellation defined in accordance with the number of phases. The data delay may be performed in the baseband or at the RF rate to time-align local oscillator clocks with the delayed data, which is represented as the calculated vector components, for transmission. Further modifications to the RF-DAC operation to facilitate operation with the multi-phase system are also disclosed.

Abstract: Performance indicator circuitry is provided for characterizing performance of a phase locked loop (PLL) in a phase path of a polar modulator or polar transmitter that is used to generate a phase modulated RF signal. The PLL includes an oscillator, a high pass path, and a low pass path. The low pass path includes a loop filter. The performance indicator circuitry includes first input circuitry and parameter calculation circuitry. The first input circuitry is configured to input a loop filter signal from the loop filter. The parameter calculation circuitry is configured to compute a value for a performance indicator based on the loop filter signal and control or characterize an aspect of operation of the PLL based on the value.