Patents by Inventor Tobias Gemmeke
Tobias Gemmeke has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180165395Abstract: A computer-implemented method for generating an advanced-on-chip-variation (AOCV) table of a cell is disclosed. In one aspect, the AOCV table contains the delay of the cell which is derived from a variation factor of a plurality of input patterns of the cell. The variation factor of each input pattern is derived from variation factors of a plurality basic elements. The variation factors of the basic elements are obtained as the result of a number of simulations. However, the number of basic elements is far lower than the number of possible cells. As such, the number of simulations that need to be performed is reduced drastically which results in a faster method.Type: ApplicationFiled: December 7, 2017Publication date: June 14, 2018Inventors: Bo Liu, Tobias Gemmeke
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Patent number: 9477419Abstract: A memory control system for controlling read and write operations of a non-volatile memory, wherein the memory control system comprises a memory controller that is adapted to implement a write operation for writing at least one block of data to the memory as a sequence of memory write and validation cycles for part of all of the data. In one example, the number of cycles is a function of the amount of successfully written data per cycle and is thus variable in dependence on the success of the data writing. The system also includes a power management unit, which is adapted to authorize or prevent the memory controller from conducting the write operation at the level of the write cycles thereby to control the timing of power consumption resulting from the cycles of the write operation.Type: GrantFiled: December 22, 2014Date of Patent: October 25, 2016Assignee: Stichting IMEC NederlandInventors: Tobias Gemmeke, Julien Penders, Carlos Agell
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Patent number: 9425795Abstract: The present disclosure relates to a detection circuit formed as part of an integrated circuit. In one example, the detection circuit includes a signal generator configured to generate a reference signal, and an amplification circuit comprising a p-channel transistor and an n-channel transistor, wherein the amplification circuit is affected by a variability that also affects a functional circuit formed as part of the integrated circuit. The variability causes the p-channel transistor and the n-channel transistor to have different respective drive strengths. The amplification circuit is configured to receive the reference signal and to provide an amplified signal representative of a difference in the respective drive strengths, wherein the reference signal is more insensitive to the variability than the amplified signal. The present disclosure also relates to an integrated circuit and a method for detecting and compensating a transistor mismatch.Type: GrantFiled: March 5, 2014Date of Patent: August 23, 2016Assignee: Stichting IMEC NederlandInventors: Maryam Ashouei, Tobias Gemmeke
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Publication number: 20160161979Abstract: A digital CMOS circuit comprising at least one pull-up circuit arranged, when in an on-state, to switch an output node of the digital CMOS circuit from a first voltage level to a second voltage level within a rising transition delay. The digital CMOS circuit further comprises at least one pull-down circuit arranged, when in an on-state, to switch the voltage level of the output node of the digital CMOS circuit from the second voltage level to the first voltage level within a falling transition delay. The digital CMOS circuit further comprises at least one performance matching transistor serially connected to the first and second type transistors, the gate terminal of which is connected to biasing means arranged for biasing the at least one performance matching transistor in such a way so as to compensate for the performance mismatch between the at least one first and second type transistors.Type: ApplicationFiled: December 4, 2015Publication date: June 9, 2016Applicant: Stichting IMEC NederlandInventor: Tobias Gemmeke
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Publication number: 20160013792Abstract: The present disclosure relates to a detection circuit formed as part of an integrated circuit. In one example, the detection circuit includes a signal generator configured to generate a reference signal, and an amplification circuit comprising a p-channel transistor and an n-channel transistor, wherein the amplification circuit is affected by a variability that also affects a functional circuit formed as part of the integrated circuit. The variability causes the p-channel transistor and the n-channel transistor to have different respective drive strengths. The amplification circuit is configured to receive the reference signal and to provide an amplified signal representative of a difference in the respective drive strengths, wherein the reference signal is more insensitive to the variability than the amplified signal. The present disclosure also relates to an integrated circuit and a method for detecting and compensating a transistor mismatch.Type: ApplicationFiled: March 5, 2014Publication date: January 14, 2016Applicant: Stichting IMEC NederlandInventors: Maryam Ashouei, Tobias Gemmeke
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Publication number: 20150309753Abstract: A memory control system for controlling read and write operations of a non-volatile memory, wherein the memory control system comprises a memory controller that is adapted to implement a write operation for writing at least one block of data to the memory as a sequence of memory write and validation cycles for part of all of the data. In one example, the number of cycles is a function of the amount of successfully written data per cycle and is thus variable in dependence on the success of the data writing. The system also includes a power management unit, which is adapted to authorize or prevent the memory controller from conducting the write operation at the level of the write cycles thereby to control the timing of power consumption resulting from the cycles of the write operation.Type: ApplicationFiled: December 22, 2014Publication date: October 29, 2015Applicant: STICHTING IMEC NEDERLANDInventors: Tobias Gemmeke, Julien Penders, Carlos Agell
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Patent number: 8860502Abstract: An apparatus for monitoring timing of a plurality of critical paths of a functional circuit includes a plurality of canary circuits, each configured to be coupled to a critical path of a functional circuit for detecting and outputting critical timing events. Each canary circuit includes an adjustable delay element and an analyzer circuit for receiving a count of the critical timing event output from at least one of the plurality of canary circuits for a predetermined time interval for a plurality of delay values of the adjustable delay elements and for determining a probability distribution of critical timing events of the at least one of the plurality of critical paths for the predetermined time interval for the plurality of delay values.Type: GrantFiled: May 10, 2013Date of Patent: October 14, 2014Assignee: Stichting IMEC NederlandInventors: Tobias Gemmeke, Mario Konijnenburg
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Patent number: 8756263Abstract: A binary logic unit to apply any Boolean operation on two input signals (va, vb) is described, wherein any Boolean operation to be applied on the input signals (va, vb) is defined by a particular combination of well defined control signals (ctl0, ctl1, ctl2, ctl3), wherein the input signals (va, vb) are used to select a control signal (ctl0, ctl1, ctl2, ctl3) as an output signal (vo) of the binary logic unit representing the result of a particular Boolean operation applied on the two input signals (va, vb). Furthermore a method to operate such a binary logic unit is described.Type: GrantFiled: January 1, 2013Date of Patent: June 17, 2014Assignee: International Business Machines CorporationInventors: Tobias Gemmeke, Jochen Preiss
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Publication number: 20130300463Abstract: An apparatus for monitoring timing of a plurality of critical paths of a functional circuit includes a plurality of canary circuits, each configured to be coupled to a critical path of a functional circuit for detecting and outputting critical timing events. Each canary circuit includes an adjustable delay element and an analyser circuit for receiving a count of the critical timing event output from at least one of the plurality of canary circuits for a predetermined time interval for a plurality of delay values of the adjustable delay elements and for determining a probability distribution of critical timing events of the at least one of the plurality of critical paths for the predetermined time interval for the plurality of delay values.Type: ApplicationFiled: May 10, 2013Publication date: November 14, 2013Applicant: Stichting IMEC NederlandInventors: Tobias Gemmeke, Mario Konijnenburg
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Patent number: 8452824Abstract: A binary logic unit to apply any Boolean operation on two input signals (va, vb) is described, wherein any Boolean operation to be applied on the input signals (va, vb) is defined by a particular combination of well defined control signals (ctl0, ctl1, ctl2, ctl3), wherein the input signals (va, vb) are used to select a control signal (ctl0, ctl1, ctl2, ctl3) as an output signal (vo) of the binary logic unit representing the result of a particular Boolean operation applied on the two input signals (va, vb). Furthermore a method to operate such a binary logic unit is described.Type: GrantFiled: October 16, 2007Date of Patent: May 28, 2013Assignee: International Business Machines CorporationInventors: Tobias Gemmeke, Jochen Preiss
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Patent number: 8370409Abstract: A method for operand width reduction is described, wherein two N-bit input operands (A, B) of a bit width of N are processed and two M-bit output operands (A?, B?) of a reduced bit width of M are generated in a way, that a post-processing comprising an M-bit adder function followed by saturation to M bits performed on said two M-bit output operands (A?, B?) provides an M-bit result equal to an M-bit result of an N-bit modulo adder function of the two N-bit input operands (A, B), followed by a saturation to M bits. Further an electronic computing circuit (1, 5) is described performing said method. Additionally a computer system comprising such an electronic computing circuit is described.Type: GrantFiled: February 11, 2008Date of Patent: February 5, 2013Assignee: International Business Machines CorporationInventors: Tobias Gemmeke, Nicolas Maeding, Jochen Preiss
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Patent number: 8312069Abstract: A permute unit includes permute logic and a crossbar working in cycles defined by clocking signals and generates one valid output vector per cycle by treating two parallel input vectors per cycle. The permute unit is double pumped by performing two inner cycles per outer cycle defined by the clocking signals. In the first inner cycle, first halves of both input vectors are treated. In the second inner cycle, second halves of both input vectors are treated and a valid output vector is generated from the results of the treatments within the first and the second inner cycles.Type: GrantFiled: October 16, 2007Date of Patent: November 13, 2012Assignee: International Business Machines CorporationInventors: Tobias Gemmeke, Jens Leenstra, Dieter Wendel
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Patent number: 8266411Abstract: Instead of having a processor with an instruction set architecture (ISA) that includes fixed architected operands, an improved processor supports additional characteristic bits for computing instructions (e.g., a multiply-add, load/store instructions). Such additional bits for the certain instructions influence the processing of these instructions by the processor. Also, a new instruction is introduced for further usage of the proposed method. Typically these additional characteristic bits as well as the instruction can be automatically generated by compilers to provide relatively well-suited instruction sequences for the processor.Type: GrantFiled: February 5, 2009Date of Patent: September 11, 2012Assignee: International Business Machines CorporationInventors: Tobias Gemmeke, Markus Kaltenbach, Nicolas Maeding
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Patent number: 7996738Abstract: A semiconductor chip subdivided into power domains, at least one of the power domains is separately activated or deactivated and at least a part of the scannable storage elements are interconnected to one or more scan chains. At least one scan chain is serially subdivided into scan chain portions and the scan chain portion is arranged within one of the power domains. For at least one scan chain portion a bypass line is provided for passing by scan data and at least one select unit is provided for selecting between the bypass line and the corresponding scan chain portion in dependence of the activated or deactivated state of the corresponding power domains.Type: GrantFiled: March 5, 2008Date of Patent: August 9, 2011Assignee: International Business Machines CorporationInventors: Tobias Gemmeke, Christoph Jaeschke, Jens Kuenzer, Cedric Lichtenau, Thomas Pflueger, Jochen Preiss
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Patent number: 7962538Abstract: An electronic computing circuit for implementing a method for reducing the bit width of two operands from a bit length N to a reduced bit length M, thus, M<N. To enable a wider re-usage of existing designs or building blocks being all specialized to the usual bit length of a power of 2 (8, 16, 32, 64 etc.), the chip structure of which is already highly optimized in regard of speed and space savings, a circuit is implemented as an addend width reduction circuit to perform the steps of: receiving said two N-bit operands as an input, adding the (N?M+1) most significant bits of said two N-bit operands separately in an auxiliary adder logic, calculating at least the two most significant bits of reduced-bit-length output operands in a decision logic processing the add result of said auxiliary adder logic, such that a predetermined post-processing can be correctly performed with said output operands.Type: GrantFiled: November 15, 2006Date of Patent: June 14, 2011Assignee: International Business Machines CorporationInventors: Tobias Gemmeke, Jens Leenstra, Nicolas Maeding, Kerstin Schelm
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Patent number: 7913132Abstract: A digital system and method for scanning sequential logic elements are disclosed. The digital system may comprise a plurality of sequential logic elements subdivided into power domains, wherein at least one of the power domains is power gated; a scan chain configured for processing a scan data sequence; a scan enable switch configured for controlling a scan mode; and at least one shadow engine, wherein the at least one shadow engine comprises a control circuit. At least some of the power domains may be interconnected to the scan chain with the scan enable switch, and the scan enable switch may control the scan mode by asserting a scan enable signal. The at least one power gated power domain with one or more sequential logic elements to be power gated may be bypassed via the at least one shadow engine.Type: GrantFiled: November 19, 2008Date of Patent: March 22, 2011Assignee: International Business Machines CorporationInventors: Tobias Gemmeke, Dieter Wendel, Holger Wetter, Jens Leenstra
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Patent number: 7890901Abstract: The automatic verification of designs of digital circuits for their equivalence, wherein logic designs implemented in different hardware description languages (HDLs) and different design methodologies are compared. The designs (Code A, Code B) are modified by adding special wrappers (Wrapper A, Wrapper B), and used to equalize the timing of pairs of selected input signals and selected output signals of the logic designs. The wrappers drive certain signals of the designs that are not relevant for actual comparison, such signals including clock signals, clock control signals, scan-path signals, scan-path control signals, and reset signals. In a preferred embodiment, HDL descriptions of logic designs are analyzed. Based on this analysis, the wrappers are implemented as changes to the HDL descriptions. In another embodiment, RTL and/or gate-level netlists are analyzed and modified.Type: GrantFiled: March 12, 2007Date of Patent: February 15, 2011Assignee: International Business Machines CorporationInventors: Tobias Gemmeke, Jens Leenstra, Nicolas Maeding, Hari Mony
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Patent number: 7849428Abstract: The present invention provides a fully automatic method for obtaining a circuit having minimized power consumption due to clock-gating. A circuit design to be optimized is modified to a reduced power modified design and associated with a clock gating scheme. Verification tools compare the modified design with the original design to a predetermined trigger-events to determine if the modified design can be used. Further modifications may be made iteratively until an optimal design is achieved.Type: GrantFiled: April 23, 2008Date of Patent: December 7, 2010Assignee: International Business Machines CorporationInventors: Harry Barowski, J. Adam Butts, Tobias Gemmeke, Nicolas Maeding, Viresh Paruthi
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Patent number: 7795914Abstract: A three stage circuit according to the invention comprises a data input, a data output, a control input, two voltage supply inputs. The first stage is electrically connected to the data input and control input and is defined by a combinatorial circuitry with two outputs. The second stage is defined by at least two transistors connected in series between the two voltage supply inputs with their inputs electrically connected to the respective outputs of the first stage and with a common output such that in connection with the first stage they operate as a tri-state gate. The third stage of that three stage circuit is electrically connected to the control input and the common output of the second stage.Type: GrantFiled: October 31, 2008Date of Patent: September 14, 2010Assignee: International Business Machines CorporationInventors: Tobias Gemmeke, Friedrich Schroeder, Stefan Bonsels, Dieter Wendel
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Publication number: 20100199074Abstract: Instead of having a processor with an instruction set architecture (ISA) that includes fixed architected operands, an improved processor supports additional characteristic bits for computing instructions (e.g., a multiply-add, load/store instructions). Such additional bits for the certain instructions influence the processing of these instructions by the processor. Also, a new instruction is introduced for further usage of the proposed method. Typically these additional characteristic bits as well as the instruction can be automatically generated by compilers to provide relatively well-suited instruction sequences for the processor.Type: ApplicationFiled: February 5, 2009Publication date: August 5, 2010Applicant: International Business Machines CorporationInventors: Tobias Gemmeke, Markus Kaltenbach, Nicolas Maeding