Patents by Inventor Tobias Kist
Tobias Kist has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230378888Abstract: An electrical system includes a power module and a DC link capacitor. The power module includes first and second facing substrates that define between them an inner space of the power module. The power module comprises switches supported by the first or second substrate and extending in the inner space of the power module, and inner electrical conductors extending in the inner space of the power module and connecting the switches. The inner electrical conductors include two inner DC electrical conductors for receiving a DC voltage (E). The DC link capacitor comprises two capacitor electrical conductors facing each other and extending at least partially outside the inner space of the power module and respectively connected to the inner DC electrical conductors for stabilizing the DC voltage (E). The electrical system comprises an overmolding encapsulating at least partially the substrates, the switches, the inner electrical conductors and the capacitor electrical conductors.Type: ApplicationFiled: September 10, 2021Publication date: November 23, 2023Applicant: Valeo eAutomotive Germany GmbHInventor: Tobias KIST
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Patent number: 11515228Abstract: A semiconductor package includes an encapsulant body; an upper electrically conductive element having an outwardly exposed metal surface; a lower carrier substrate having an upper electrically conductive layer, a lower electrically conductive layer having an outwardly exposed surface, and an electrical insulation layer; a first electrically conductive spacer between the upper electrically conductive element and the upper electrically conductive layer; a power semiconductor chip between the upper electrically conductive element and the upper electrically conductive layer; and a second electrically conductive spacer between the upper electrically conductive element and the power semiconductor chip, a first carrier region of the upper electrically conductive layer is connected to a first power terminal, a second carrier region of the upper electrically conductive layer is alongside the first carrier region and is connected to a phase terminal, a first region of the upper electrically conductive element is connecType: GrantFiled: January 13, 2021Date of Patent: November 29, 2022Assignee: Infineon Technologies AGInventors: Juergen Hoegerl, Ordwin Haase, Tobias Kist
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Publication number: 20220319948Abstract: A semiconductor package includes an encapsulant body; a first electrically conductive element having an outwardly exposed metal surface; a first carrier substrate having a first electrically conductive layer, a second electrically conductive layer having an outwardly exposed surface, and an electrical insulation layer; a first electrically conductive spacer between the first electrically conductive element and the first electrically conductive layer; a power semiconductor chip between the first electrically conductive element and the first electrically conductive layer; and a second electrically conductive spacer between the first electrically conductive element and the power semiconductor chip, a first carrier region of the first electrically conductive layer is connected to a first power terminal, a second carrier region of the first electrically conductive layer is alongside the first carrier region and is connected to a second power terminal, a first region of the first electrically conductive element isType: ApplicationFiled: June 20, 2022Publication date: October 6, 2022Inventors: Juergen Hoegerl, Ordwin Haase, Tobias Kist
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Patent number: 11217504Abstract: A double-sided coolable semiconductor package includes an upper electrically conductive element having an outwardly exposed metal surface, a lower carrier substrate having an upper electrically conductive layer, a lower electrically conductive layer with an outwardly exposed surface and an electrical insulating layer arranged between the upper and lower electrically conductive layers, a first electrically conductive spacer arranged between the upper electrically conductive element and the upper electrically conductive layer, a power semiconductor chip arranged between the upper electrically conductive element and the upper electrically conductive layer, a second electrically conductive spacer arranged between the upper electrically conductive element and the power semiconductor chip, and a passive electrical component electrically connected to the upper electrically conductive layer of the lower carrier substrate.Type: GrantFiled: July 23, 2019Date of Patent: January 4, 2022Assignee: Infineon Technologies AGInventors: Juergen Hoegerl, Ordwin Haase, Tobias Kist
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Patent number: 11018072Abstract: A semiconductor package includes an upper electrically conductive element having a lower carrier substrate having an upper electrically conductive layer, a lower electrically conductive layer having an outwardly exposed surface, and an electrical insulation layer arranged between the electrically conductive layers, a first electrically conductive spacer arranged between the upper electrically conductive element and the upper electrically conductive layer, a power semiconductor chip arranged between the upper electrically conductive element and the upper electrically conductive layer, and a second electrically conductive spacer arranged between the upper electrically conductive element and the chip. A first carrier region of the upper electrically conductive layer is configured to apply a positive supply voltage. A second carrier region alongside the first carrier region is configured as a phase.Type: GrantFiled: July 23, 2019Date of Patent: May 25, 2021Assignee: Infineon Technologies AGInventors: Juergen Hoegerl, Ordwin Haase, Tobias Kist
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Publication number: 20210134697Abstract: A semiconductor package includes an encapsulant body; an upper electrically conductive element having an outwardly exposed metal surface; a lower carrier substrate having an upper electrically conductive layer, a lower electrically conductive layer having an outwardly exposed surface, and an electrical insulation layer; a first electrically conductive spacer between the upper electrically conductive element and the upper electrically conductive layer; a power semiconductor chip between the upper electrically conductive element and the upper electrically conductive layer; and a second electrically conductive spacer between the upper electrically conductive element and the power semiconductor chip, a first carrier region of the upper electrically conductive layer is connected to a first power terminal, a second carrier region of the upper electrically conductive layer is alongside the first carrier region and is connected to a phase terminal, a first region of the upper electrically conductive element is connecType: ApplicationFiled: January 13, 2021Publication date: May 6, 2021Inventors: Juergen Hoegerl, Ordwin Haase, Tobias Kist
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Patent number: 10985110Abstract: A semiconductor package having a double-sided cooling structure includes an upper electrically conductive element having an outwardly exposed metal surface, a lower carrier substrate having an upper electrically conductive layer, a lower electrically conductive layer having an outwardly exposed surface, and an electrical insulation layer arranged between the upper and lower electrically conductive layers, a first electrically conductive spacer arranged between the upper electrically conductive element and the upper electrically conductive layer, a power semiconductor chip arranged between the upper electrically conductive element and the upper electrically conductive layer, a second electrically conductive spacer arranged between the upper electrically conductive element and the power semiconductor chip, and a shielding structure configured to electromagnetically shield a line of the semiconductor package.Type: GrantFiled: July 23, 2019Date of Patent: April 20, 2021Assignee: Infineon Technologies AGInventors: Juergen Hoegerl, Ordwin Haase, Tobias Kist
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Publication number: 20200035580Abstract: A semiconductor package includes an upper electrically conductive element having a lower carrier substrate having an upper electrically conductive layer, a lower electrically conductive layer having an outwardly exposed surface, and an electrical insulation layer arranged between the electrically conductive layers, a first electrically conductive spacer arranged between the upper electrically conductive element and the upper electrically conductive layer, a power semiconductor chip arranged between the upper electrically conductive element and the upper electrically conductive layer, and a second electrically conductive spacer arranged between the upper electrically conductive element and the chip. A first carrier region of the upper electrically conductive layer is configured to apply a positive supply voltage. A second carrier region alongside the first carrier region is configured as a phase.Type: ApplicationFiled: July 23, 2019Publication date: January 30, 2020Inventors: Juergen Hoegerl, Ordwin Haase, Tobias Kist
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Publication number: 20200035581Abstract: A double-sided coolable semiconductor package includes an upper electrically conductive element having an outwardly exposed metal surface, a lower carrier substrate having an upper electrically conductive layer, a lower electrically conductive layer with an outwardly exposed surface and an electrical insulating layer arranged between the upper and lower electrically conductive layers, a first electrically conductive spacer arranged between the upper electrically conductive element and the upper electrically conductive layer, a power semiconductor chip arranged between the upper electrically conductive element and the upper electrically conductive layer, a second electrically conductive spacer arranged between the upper electrically conductive element and the power semiconductor chip, and a passive electrical component electrically connected to the upper electrically conductive layer of the lower carrier substrate.Type: ApplicationFiled: July 23, 2019Publication date: January 30, 2020Inventors: Juergen Hoegerl, Ordwin Haase, Tobias Kist
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Publication number: 20200035616Abstract: A semiconductor package having a double-sided cooling structure includes an upper electrically conductive element having an outwardly exposed metal surface, a lower carrier substrate having an upper electrically conductive layer, a lower electrically conductive layer having an outwardly exposed surface, and an electrical insulation layer arranged between the upper and lower electrically conductive layers, a first electrically conductive spacer arranged between the upper electrically conductive element and the upper electrically conductive layer, a power semiconductor chip arranged between the upper electrically conductive element and the upper electrically conductive layer, a second electrically conductive spacer arranged between the upper electrically conductive element and the power semiconductor chip, and a shielding structure configured to electromagnetically shield a line of the semiconductor package.Type: ApplicationFiled: July 23, 2019Publication date: January 30, 2020Inventors: Juergen Hoegerl, Ordwin Haase, Tobias Kist