Abstract: The invention relates to a road finishing machine with a controllable longitudinal conveyor device and a transverse conveyor device for mixed laying material disposed in the rear in the direction of motion. The road finishing machine furthermore comprises a control unit for adjusting a delivery rate of the longitudinal conveyor device and/or the transverse conveyor device. The control unit is connected with a sensory mechanism for determining a mixed laying material quantity or rate and adjusts the delivery rate in response to a signal from the sensory mechanism representing the mixed laying material quantity or rate. The control unit can be pilot controlled in response to laying parameters by a pilot control unit.

Abstract: The present invention describes a construction machine with a drive unit and with a cooling system that comprises a fan. The fan is connected to the drive unit by means of a controllable viscous coupling, whereby the viscous coupling can be adjusted in such a way that a required fan rotational speed is set on the output side. The invention furthermore describes a method for the automatic fan rotational speed regulation for a cooling system in a construction machine.

Abstract: In a road finishing machine with a primary power plant and a power transfer to a hydraulic pump and/or a generator for supplying power to hydraulically or electrically operated functional components, the power transfer comprises at least one clutch that can be optionally engaged and disengaged, and a clutch control device is provided by means of which, depending on at least the operator guidance and/or a detected clutch loading situation, a disengagement delay (?t) automatically overriding the operator guidance can be set, and/or a clutch shifting number restriction can be set by means of a detection interval (dt) moving along in time. The clutch control device actually engages, within the frame of the respective overriding control strategy, the clutch only after the disengagement delay (?t) has lapsed, if no operation command to the contrary is present, and/or keeps the clutch first engaged, although an operation command to the contrary is present.

Abstract: In the hydrostatic working operation of a road finishing machine or a feeder which comprises a primary power plant with an internal combustion engine (M) and several hydraulic variable displacement pumps, which are hydraulically connected to hydraulic motors of working components, and which possesses a computerized control device, the internal combustion engine is operated within its engine-specific characteristic map in response to the load condition by dynamic speed adaptation in a characteristic zone with optimal consumption, and the displacements (VsHP) of the variable displacement pumps are simultaneously automatically adapted for keeping the volume flow rates for the hydraulic motors constant.

Abstract: The invention relates to a self-propelling machine for processing bituminous or concrete pavement material, in particular a road finisher or a feeder. The machine comprises an internal combustion engine as a primary drive source, a controller for the engine, said controller receiving control signals, at least one additional drive unit for functional and operational components of the machine as well as at least one hydraulic circuit comprising a hydraulic medium reservoir. The invention is characterized in that the controller is configured for automatically causing starting and/or stopping of the engine in response to receipt of at least one specific control signal.

Abstract: In a self-propelled machine F for processing paving material, the machine having a liquid cooled combustion engine M and at least one hydraulic circuit H containing hydraulic pumps 6, hydromotors or hydrostatic drive units 7-10 and at least one hydraulic medium reservoir 12, a fan assisted cooling device K including cooling regions 1b, 1c at least for the cooling liquid of the combustion engine M and of the hydraulic medium of the hydraulic circuit H. A hydraulic medium operation temperature setting and regulating device R is provided for the hydraulic medium cooling region 1c constituted by a separate cooler 24 in order to generate an operation temperature T of the hydraulic medium above at least about 60° C. and to maintain this operation temperature depending on the hydraulic load situation in the hydraulic liquid H and on the surrounding climate, independently from a cooling regulating system S for the combustion engine M.

Abstract: An apparatus has a clock monitoring device, which determines whether or not the clock rate of an input clock signal (.PHI..sub.0) has fallen below a predetermined minimum clock rate. A system is provided which, from the input clock signal, forms a master clock signal (.PHI..sub.m) and a slave clock signal (.PHI..sub.s) which are in a form such that both the switches (S1) of dynamic master registers (ML) and the switches (S2) of dynamic slave registers (SL) are closed provided that the clock rate has fallen below the minimum clock rate. Otherwise, at most either the switches (S1) of the dynamic master latches (ML) or the switches (S2) of the dynamic slave latches (SL) are closed. The primary advantage achieved hereby is that in the event of failure of the input clock signal, in particular in circuits with a high degree of pipelining, undefined register states do not result in an impermissibly high current consumption.

Abstract: A method for manufacturing multichip modules having layer sequences made of dielectric material with conducting tracks embedded therein is characterized by the following features: (1) a temperature-resistant, base-resistant polymer having a dielectric constant .ltoreq.3 is used as a dielectric material, which is applied to a non-conductive substrate and serves as an edge boundary for currentless, autocatalytic build-up of the conducting tracks; (2) the dielectric material is provided with a layer made of material which is soluble in organic solvents (lift-off layer); (3) the dielectric material and the lift-off layer are structured in a single lithographic step, either a direct or an indirect structuring taking place and grooves having an aspect ratio .gtoreq.

Abstract: A CORDIC processor is provided in carry-save architecture in connection with intense pipelining for vector rotations, particularly given problems in real-time processing. The processor comprises a plurality of vector iteration stages and a plurality of angle iteration stages that are partially redundantly present in order to guarantee a convergency of the CORDIC algorithm despite an ambiguity region in the sign detection of carry-save numbers and in order to simplify other circuit components, for example a multiplier. As a result of the carry-save architecture, only incomplete addition/subtraction operations are executed in the iteration stages, and intermediate results in the form of carry and save words are fed through the CORDIC processor on separate line paths until they are added in an adder at the processor output to form the final result vector.

Abstract: A digital decimation filter which includes a multiplexer which receives signal values x.sub.i at a sampling rate of 1/T and where output signals which have half the sampling rate are supplied to two outputs. Separate bit associated circuits BP1 and BP2 are connected to the outputs for each significant figure of the p-place binary filter coefficients c6 through c1 and each of the bit associated circuits include partial products stages Mc6.sub.0 . . . Mc1.sub.0, Mc6.sub.1 . . . Mc1.sub.1 for all of the filter coefficient bits and the bit associated circuits also contain adder-register iterative circuits including delay elements and the output of the iterative circuit of the most significant bit plane BP2 is the output of the filter.

Abstract: A series of adders (AD.sub.i) with inputs for binary number bits of the same significance, which output intermediate sum and carry words that are combined to form sum words, are provided for the bit-parallel addition of binary numbers in two's complement with carry-save overflow correction. For the correction of overflow errors, the carry bit of the adder (AD.sub.n-2) having the second highest significance is replaced by the carry bit of the most significant adder (AD.sub.n-1) and, in case the carry bits of the two most significant adders (AD.sub.n-1, AD.sub.n-2) are unequal, the intermediate sum bit of the most significant adder (AD.sub.n-1) is replaced by the carry bit thereof. The element AD.sub.kn-1 has the same number of transistors as the other adders AD.sub.0 . . . AD.sub.n-2.

Abstract: A circuit for the multiplication of the elements of a multiplicand matrix represented by first digital signals by the elements of a multiplier matrix represented by second digital signals. A multiplicand line is provided for every row of the multiplicand matrix and the individual sections (L11. . . L14) o f these multiplicand lines are connected to bit-associated circuits (bit planes) (BP1. . . BP4). Every bit plane contains the partial product stages (1, 2, 3) which are allocated to the bits of the second digital signals having a defined significance, and also contain an iterative circuit composed of adders (4, 5) and time delay elements (6, 7, 8) in an alternating arrangement.

Abstract: In an arrangement for the bit-parallel addition of binary numbers in two's complement form, a series of adders (AD.sub.i) are provided to receive inputs for binary bits of equivalent significance and to emit intermediate sum and carry words which are combined to form result sum words. For the correction of overflow errors, the carry bit of the adder (AD.sub.n-2) having the second highest significance is replaced by the carry bit of the most significant adder (AD.sub.n-1) and, when the carry bits of the two most significant adders (AD.sub.n-1, AD.sub.n-2) are unequal, the intermediate sum bit of the most significant adder (AD.sub.n-1) is replaced by its carry bit.

Abstract: A carry-save adder for a bit-parallel addition of binary numbers in two's complement form incorporates a series of first adders for forming intermediate sum and carry words which are combined in an adder means to form a sum word. A decoder is provided for recognizing saturation of the carry-save adder and for generating overflow signals in dependence on the two most significant bits of the intermediate sum and carry words. When the overflow signals are generated, the recursive circuit branches are disconnected and saturation intermediate sum and carry words are substituted for the intermediate sum and carry words which yield sum words which do not exceed the permissible adder content.

Abstract: A digital multiplier which has cells arranged in a plurality of rows and columns wherein the rows are assigned to different groups of partial product bits. Sum paths and carry paths are provided which connect the individual cells to each other and at their ends emit signals from which the product bits are formed. The multiplicand bits are stored intermediately together with the sum and carry signals formed in a row and are simultaneously forwarded to the next row in accordance with a pipelining process. It is desired to obtained the least possible delay in feeding a multiplier bit into all the cells of a row so as to achieve short range transit time of the signals between the output of two consecutive rows and this is achieved with a logic link element which is used to form a partial product bit which is contained in a cell which proceeds the row and in which this partial product bit is added to sum signals and carry signals.

Abstract: A digital arithmetic unit useful in data processing digital circuits comprises a plurality of stages each having two half-adders combined into a full adder and a carry logic element. An objective is to shorten the processing time for the addition and subtraction of binary numbers. For this purpose, the stages are divided into at least two groups and two separate carry paths are provided within each group. One of the carry paths is only switched on by means of selection logic elements. The activation occurs sequentially in group-wise fashion after simultaneous carry runs in all carry paths. The advantage particularly consists of the chronological coincidence of the carry runs in all groups.