Abstract: A system including a power device for wireless charging of a battery of a portable device, and the power device has an antenna to emit a magnetic field with a carrier frequency to power the portable device which includes an antenna exposed to the magnetic field and connected via a matching stage to a rectifier stage, to rectify an antenna signal, and the portable device comprises a charge stage, to sense and limit the rectified antenna signal. The portable device includes a detuning stage to change the resonance frequency of the antenna of the portable device and that the charge stage is configured to limit the input voltage (UI) for the charger IC by steering the detuning stage to detune the resonance frequency of the antenna of the portable device away from the carrier frequency of the magnetic field.

Abstract: A system of a power device and a portable device for wireless charging of a battery of the portable device. The power device includes an antenna to receive power adjustment information to increase or to decrease the power of the magnetic field emitted by the antenna of the power device and an antenna exposed to the magnetic field and connected via a matching stage to a rectifier stage. The portable device includes a voltage limiter, to limit the rectified antenna signal, and to provide an input voltage at an input pin of a charger IC. A charge voltage control stage is built to generate the power adjustment information for the power device to increase or to decrease the power of the magnetic field emitted by the antenna of the power device to steer the waste current within an upper limit and a lower limit.

Abstract: Test reading apparatus having a memory device having individual memory cells, a buffer device, which is connected to the memory device, and which stores data written to the memory cells in the memory device, an apparatus which has an input and an output, at least one test reference source which can be connected to the input of the apparatus by data stored in the buffer device, and a test apparatus, which is connected to the buffer device and to the output of the apparatus, and which is designed to compare a signal at the output of the apparatus with data stored in the buffer device.

Abstract: Test reading apparatus having a memory device having individual memory cells, a buffer device, which is connected to the memory device, and which stores data written to the memory cells in the memory device, an apparatus which has an input and an output, at least one test reference source which can be connected to the input of the apparatus by data stored in the buffer device, and a test apparatus, which is connected to the buffer device and to the output of the apparatus, and which is designed to compare a signal at the output of the apparatus with data stored in the buffer device.

Abstract: The invention provides a circuit configuration for demodulating a voltage that is ASK modulated by altering the amplitude between a low level and a high level. In this case, a first and a second charging circuit each produce a charging voltage and decoupling device decouples the first charging circuit when there is a prescribed ratio between the charging voltage of the second charging circuit and an input voltage for the rectifier circuit.

Abstract: The invention provides a circuit configuration for demodulating a voltage that is ASK modulated by altering the amplitude between a low level and a high level. In this case, a first and a second charging circuit each produce a charging voltage and a decoupling device decouples the first charging circuit when there is a prescribed ratio between the charging voltage of the second charging circuit and an input voltage for the rectifier circuit.

Abstract: A configuration is described for evaluating a signal that is read from a ferroelectric storage capacitor, in which, in addition to positive and negative polarization states, a weak polarization state is evaluated. Using the configuration, a data storage characteristic of the memory cells can be monitored, and a manipulation attempt can be detected.

Abstract: A configuration is described for evaluating a signal that is read from a ferroelectric storage capacitor, in which, in addition to positive and negative polarization states, a weak polarization state is evaluated. Using the configuration, a data storage characteristic of the memory cells can be monitored, and a manipulation attempt can be detected.

Abstract: An integrated memory in which the plate lines run parallel to the bit lines and are driven by the column decoder. The effect achieved by the fact that each plate line is connected to the memory cells of the associated bit line is that only those memory cells whose associated bit line is required for the respective memory access are affected by the pulsed signals of the plate line. Therefore, only the potential of that bit line which is currently required for a data transfer is influenced by pulsed signals on the associated plate lines.

Abstract: An integrated memory in which the plate lines run parallel to the bit lines and are driven by the column decoder. The effect achieved by the fact that each plate line is connected to the memory cells of the associated bit line is that only those memory cells whose associated bit line is required for the respective memory access are affected by the pulsed signals of the plate line. Therefore, only the potential of that bit line which is currently required for a data transfer is influenced by pulsed signals on the associated plate lines.

Abstract: An integrated memory includes word lines and bit lines intersecting each other at crossover points. The bit lines are combined into bit line pairs and the bit line pairs are interleaved by having at least one of the bit lines of one bit line pair disposed between the two bit lines of another bit line pair. 2-transistor/2-capacitor memory cells each have two 1-transistor/1-capacitor memory cells each disposed at a respective one of the crossover points. Each of the two 1-transistor/1-capacitor memory cells of the 2-transistor/2capacitor memory cells have a selection transistor connected to one of the two bit lines of a respective one of the bit line pairs and to at least one of the word lines. The selection transistors may be simultaneously activated for simultaneously accessing the two 1-transistor/1-capacitor memory cells of one of the 2-transistor/2-capacitor memory cell.

Abstract: The memory has a control unit, which, in order to generate a common reference potential on the two bit lines, turns on the first switching element and the selection transistors of the two reference memory cells and, after a specific time period, turns off the selection transistors, while the first switching element remains in the on state and compensates for a potential difference between the two bit lines.

Abstract: An integrated memory having a first wiring plane with parallel conductor tracks running therein. A second wiring plane in the memory has segments running in it that are parallel to the conductor tracks. Word lines are each formed by a conductor track of a first type and by segments configured parallel to this conductor track. A conductor track of a second type is connected to a first supply line and to regions that are configured in a third wiring plane within the cell array.