Abstract: A device includes a first radio controller configured to communicate using a first protocol, and a pseudo random number generator configured to generate a pseudo random output value based on an input data value. The device includes a processor configured to determine a preamble code based on an output of the pseudo random number generator, and process a data packet received using the first radio controller using the preamble code to generate a processed data packet.

Abstract: One example securely updates an integrated circuit to mitigate undesirable modifications and this involves an application circuit accessing an external network while a (e.g., nonvolatile) program memory is write protected; and a reset-boot circuit resetting and booting the application circuit while access to the external network is disabled, and causing an update for the application circuit. In response to an indication that an update is downloaded for installation, the downloaded update is installed in the memory while access to the external network is disabled, and execution of the reset mode is permitted after the update is installed. Also, a retrieval module may download, in response to an indication that an update is not downloaded, an update provided via the external network while the memory is write-protected and thereby permitting execution of the reset mode after the update is downloaded.

Abstract: The present invention relates to bacteriocins for control of Salmonella enterica (salmocins). The bacteriocins are derived from Salmonella. The salmocins can be expressed in plants and can be used in a method of preventing or reducing infection or contamination of an object with Salmonella.

Abstract: A method for checking a computation of a discrete Fourier transform (DFT), including: computing a first layer of the DFT using a plurality of butterfly operations on inputs to the first layer to produce first outputs; computing a second layer of the DFT using a plurality of butterfly operations on the first outputs to produce second outputs; performing an invariant check on the first outputs after the computation of the second layer based upon the inputs to the first layer; and indicating a fault in the computation of the DFT when the invariant check fails.

Abstract: A method of performing a Dilithium signature operation on a message M using a secret key sk, including: calculating a value {tilde over (r)} based upon w0, c, and s2, where w0 and c are calculated as part of the Dilithium signature operation and s2 is part of the secret key sk; performing a bound check on {tilde over (r)} based upon ?2 and ?, where ?2 and ? are parameters of the Dilithium signature operation; calculating a hint h based on the value {tilde over (r)} and deleting the value {tilde over (r)} in a memory; regenerating a value y using an ExpandMask function; calculating z based upon y, c, and s1, where s1 is part of the secret key sk and replacing y with z in the memory; performing a bound check on z based on ?1 and ?, where ?1 is a parameter of the Dilithium signature operation; and returning a digital signature of the message M where the digital signature includes z and h.

Abstract: A method of performing a Dilithium signature operation on a message M using a secret key sk, including: generating a polynomial y using an ExpandMask function; calculating a polynomial z based upon y, c, and s1; performing a bound check on z based upon ?1 and ?; performing a bound check on ct0 based upon ?2; calculating a polynomial {tilde over (r)} based upon A, z, c, t, ?, and w1; performing a bound check on {tilde over (r)} based upon ?2 and ?; calculating a hint polynomial h based on the {tilde over (r)}; and returning a digital signature of the message M where the digital signature includes z and h.

Abstract: A method is provided to protect a stack of return addresses from manipulation. The return address indicates where to return in a computer program after a subroutine is called. In the method, an encryption key and an initial tweak value is selected. For a return address to be stored on the stack, a first chained address is generated by encrypting the return address with the encryption key and the initial tweak value. The first chained address is provided to the stack instead of the return address. For a subsequent return address that is subsequent to the return address, a second chained address is generated by encrypting the subsequent return address with the encryption key and the first chained address. The second chained address is provided to the stack instead of the subsequent return address. The method provides effective protection without requiring additional memory in a memory limited system.

Abstract: A data processing system comprising instructions embodied in a non-transitory computer readable medium, the instructions for a cryptographic operation using polynomials for lattice-based cryptography in a processor, the instructions, including: applying a share-wise Kronecker substitution to arithmetic shares of a first polynomial; applying a Kronecker substitution to a second polynomial; multiplying share-wise the Kronecker substitution of the second polynomial and the arithmetic shares of the Kronecker substitution of the shares of the first polynomial to produce arithmetic shares of a first output; converting the shares of the first output to arithmetic shares of a polynomial representation; converting the arithmetic shares of the polynomial representation to Boolean shares of the polynomial representation; adding the Boolean shares of the polynomial representation to Boolean shares of a third polynomial to produce Boolean shares of a second output; and carrying out a cryptographic operation using the Bool

Abstract: A secure processing system configured to produce a hash based digital signature of a message, including: random number generator (RNG); a monotonic counter device configured to produce a monotonically increasing counter value; a hash accelerator configured to produce a hash of the message based upon a random number from the RNG and the counter value; and a run time integrity check (RTIC) device configured to check the integrity of the operation of the hash accelerator based upon the counter value.

Abstract: Various embodiments relate to a fault detection system and method for a digital signature algorithm, including: producing a digital signature of a message using a digital signature algorithm; storing parameters from a last round of the digital signature algorithm; executing the last round of the digital signature algorithm using the stored parameters to produce a check signature; comparing the digital signature to the check signature; and outputting the digital signature when the digital signature is the same as the check signature.

Abstract: A device includes a computer readable memory storing a plurality of one-time signature (OTS) keypairs and a processor that is configured to execute a hash function on a message using a first private key of a first OTS keypair of the plurality of OTS keypairs to determine a message signature, execute the hash function to calculate a leaf node value of a hash tree using the first OTS keypair, determine a plurality of authentication path nodes in the hash tree, retrieve, from the computer readable memory, values of a first subset of the plurality of authentication path nodes, calculate values for each node in a second subset of the plurality of authentication path nodes, and store, in the computer readable memory, the values for each node in the authentication path and the value of the leaf node.

Abstract: Various embodiments relate to a data processing system including instructions embodied in a non-transitory computer readable medium, the instructions for a cryptographic operation using masked coefficients of a polynomial having d arithmetic shares for lattice-based cryptography in a processor, the instructions, including: shifting an arithmetic share of the d arithmetic shares by a first bound ?0; converting the d shifted arithmetic shares to d Boolean shares; securely subtracting the first bound ?0 and a second bound ?1 from the Boolean shares to obtain z?B,k+1 having d shares, wherein k is the number of bits in the masked coefficients of the polynomial; setting the shares of a boundary check bit to a sign bit of z?B,k+1; and carrying out a cryptographic operation using the d arithmetic shares of the polynomial when the d shares of the boundary check bit indicate that the coefficients of the polynomial are within the first bound ?0 and second bound ?1.

Abstract: A curved light guide structure configured to guide a spectral region, includes: end faces disposed at two ends of the ring segment structure; a first main side extending between the end faces and a second main side opposite the first main side and extending between the end faces; at least a first pass region on the first main side, the first pass region being configured to receive and let pass an optical signal within the spectral region, the curved light guide structure being configured to guide the optical signal along an axial direction between the end faces; and at least a second pass region on the second main side that is configured to let pass and to emit at least part of the optical signal from the curved light guide structure.

Abstract: A system and method of carrying out a binary arithmetic operation in a cryptographic operation for lattice-based cryptography. The variables used in the binary arithmetic operation may have their bits randomly rotated to counter side channel attacks. An addition and multiplication operation on variables with rotated bits are disclosed.

Abstract: A data processing system comprising instructions embodied in a non-transitory computer readable medium, the instructions for generating keys in a hash based signature system in a processor, the instructions, including: generating, by a random number generator, a seed; repeatedly hashing the seed with a first hash function to produce n/k chained seeds, wherein n is a total number secret keys generated and k is a number of secret keys generated from each chained seed; and generating k secret keys from each of the n/k chained seeds using a second hash function, wherein at least one of the k secret keys is generated from another of the k secret keys in a sequential chain.

Abstract: A data processing system and method for norm checking a cryptographic operation for lattice-based cryptography in a processor, the instructions, including: multiplying a first polynomial by a second polynomial to produce a first output, wherein the d arithmetic shares have a modulus q?; securely converting the first output to d Boolean shares; securely subtracting a third polynomial from the first output to produce a second output, wherein the third polynomial is randomly generated and then offset by a first constant parameter; securely adding a first constant based upon a bound check and the first constant parameter to the second output to shift the values of the second output to positive values to produce a third output; and securely adding a second constant based upon the bound check to the third output to produce a carry bit.

Abstract: A communication node for optical-wireless communication in an optical-wireless communication network has: an input interface configured to receive a data signal, an optical transmitter configured to convert the data signal into an optical signal having an optical power, separation optics configured to spatially divide the optical signal into a plurality of optical partial signals having an associated spectral range to divide the optical power onto the plurality of optical partial signals, wherein the plurality of spectral ranges at least partially match. The communication node is configured to emit the plurality of optical partial signals for optical-wireless communication.

Abstract: A hardware converter configured to convert d arithmetic shares of x to d Boolean shares of x. The hardware converter has a plurality of addition layers in a tree structure. Each layer has a plurality of secure bit adders.

Abstract: A plurality of objects that comprise an input to a cryptographic signing function. For each object in the plurality of objects, an output value yi of a hash function is calculated, where the value i is equal to an index value of the object, a compressed output value xi of a compression function is calculated, the output value yi from the computer readable memory, and the compressed output value xi is stored. For each object in the plurality of objects, an output value y?i of the hash function is calculated, where the value i is equal to the index value of the object, a compressed output value x?i of the compression function executed on the output value y?i is calculated, the output value x?i is determined to be equal to the output value xi, and the output value y?i is transmitted in an output data stream.

Abstract: A data processing system comprising instructions embodied in a non-transitory computer readable medium, the instructions for a fault detection in a digital signature algorithm in a processor, the instructions, including: computing vector z based on a secret nonce vector y, a first secret key vector s1, and a challenge polynomial c, wherein vectors z, y, and s1 include l polynomials having n coefficients, wherein polynomial c has n coefficients, and wherein l and n are integers; computing a difference value between all of the coefficients of the polynomials in the vector z; computing a number of how many of the computed difference values are outside a specified value range; computing a digital signature for an input message; and rejecting the digital signature when the computed number is greater than a threshold value.