Patents by Inventor Tobias Schuele

Tobias Schuele has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10031731
    Abstract: A method is provided for checking invariants in parallel programs using dynamic instrumentation. Invariants are provided in the source code as conventional functions and can be activated or deactivated by a user. The program is instrumented prior to or during execution of the program to allow interception of an access to the main memory unit. The addresses of the memory locations on which an invariant is dependent are automatically recorded to allow a determination of changes to the addresses. A central data structure stores an invariant for each thread, associated memory address locations, and a Boolean value indicating whether the recording process is active. A corresponding library function is requested for each load command and each storage command via the instrumentation, records the respective addresses in the event of loading commands as long as the recording process is activated, and checks the respective invariants in the event of storage commands.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: July 24, 2018
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventor: Tobias Schuele
  • Publication number: 20170123770
    Abstract: A method is provided for checking invariants in parallel programs using dynamic instrumentation. Invariants are provided in the source code as conventional functions and can be activated or deactivated by a user. The program is instrumented prior to or during execution of the program to allow interception of an access to the main memory unit. The addresses of the memory locations on which an invariant is dependent are automatically recorded to allow a determination of changes to the addresses. A central data structure stores an invariant for each thread, associated memory address locations, and a Boolean value indicating whether the recording process is active. A corresponding library function is requested for each load command and each storage command via the instrumentation, records the respective addresses in the event of loading commands as long as the recording process is activated, and checks the respective invariants in the event of storage commands.
    Type: Application
    Filed: April 7, 2015
    Publication date: May 4, 2017
    Applicant: Siemens Aktiengesellschaft
    Inventor: Tobias Schuele
  • Patent number: 9317346
    Abstract: Transmitting data elements from source threads to sink threads, which are executed on a plurality of processor cores of a parallel computer system, by using at least one global logical queue, the at least one global logical queue including an associated physical queue for each of the plurality of processor cores and a data element management table that stores, for each source thread executed on a processor core, a count that specifies a total number of data elements that are enqueued by the respective source thread and that are located in one of the physical queues of the at least one global logical queue, and a processor core index that specifies a specific processor core associated with a physical queue that contains the data elements enqueued by the respective source thread.
    Type: Grant
    Filed: February 19, 2014
    Date of Patent: April 19, 2016
    Assignee: SIEMENS AKTIENGESELLSCHAFT
    Inventor: Tobias Schüle
  • Publication number: 20160041855
    Abstract: Transmitting data elements from source threads to sink threads, which are executed on a plurality of processor cores of a parallel computer system, by using at least one global logical queue, the at least one global logical queue including an associated physical queue for each of the plurality of processor cores and a data element management table that stores, for each source thread executed on a processor core, a count that specifies a total number of data elements that are enqueued by the respective source thread and that are located in one of the physical queues of the at least one global logical queue, and a processor core index that specifies a specific processor core associated with a physical queue that contains the data elements enqueued by the respective source thread.
    Type: Application
    Filed: February 19, 2014
    Publication date: February 11, 2016
    Applicant: SIEMENS AKTIENGESELLSCHAFT
    Inventor: Tobias SCHÜLE
  • Publication number: 20150242963
    Abstract: The embodiments relate to a method for electronically representing an account movement. The method includes representing an account movement with at least the following information elements: (1) date of the account movement, (2) reason for the account movement, and (3) amount of the sum of money involved in the account movement. The method further includes representing a further information element that may be used to obtain the information about the location at which a monetary transaction on which the account movement is based took place. The embodiments also relate to an apparatus for ascertaining data for the representation of an account movement and to a communication terminal.
    Type: Application
    Filed: February 26, 2015
    Publication date: August 27, 2015
    Inventor: Tobias Schüle
  • Publication number: 20130232471
    Abstract: A method for assessing software parallelization may include the steps of analyzing the structure of a software code, splitting the software code into a multiplicity of code portions based on the structure of the software code, ascertaining a complexity value based on the analysis of the structure of the software code for each of the multiplicity of code portions, ascertaining an effort value based on the complexity value for each of the code portions, wherein the effort value indicates the effort required for parallelizing the code potion, and ascertaining an efficiency value for each of the multiplicity of code portions, wherein the efficiency value assesses the efficiency of parallelization of each of the multiplicity of code portions based on a ratio between the ascertained effort value and a useful value which indicates the expected performance gain as a result of the parallelization of the respective code portion.
    Type: Application
    Filed: October 27, 2011
    Publication date: September 5, 2013
    Inventors: Thomas Henties, Tobias Schüle