Abstract: Embodiments include method, systems and computer program products for compressing instrumentation data. Aspects include defining an intermediate region of memory. Instrumentation data associated with a processing device is received and stored in the intermediate region of the memory. The instrumentation data is compressed in the intermediate region of memory and stored in a sample region of memory.

Abstract: A method for distributed training in a parameter dataset; the method for at least one coordinating node; a network of at least one distributed node; receiving a parameter dataset from a first distributed node; decrypting the received dataset; training the parameter dataset based on a training data record to obtain a trained parameter dataset; and forwarding the trained parameter dataset to a second distributed node.

Abstract: Secure operations are performed on encrypted code. A processor in a first operating mode obtains encrypted code. The processor switches from the first operating mode to a second operating mode, and decrypts the encrypted code to obtain decrypted code. The decrypted code is executed, based on the processor being in the second operating mode, to provide a result. The result is encrypted, and the encrypted result is sent to a user, based on the processor switching back to the first operating mode.

Abstract: Embodiments of the invention are directed to methods for improving performance of a multi-core processor. A non-limiting method includes increasing a first operating frequency to a first elevated operating frequency of a first core of a gang of cores, the gang of cores comprising a plurality of cores of the multi-core processor. The method further includes upon a determination that an operating temperature of the first core is above a threshold temperature, switching processing of a thread from the first core to a second core in the gang of cores. The method further includes reducing the first operating frequency of the first core. The method further includes increasing the operating frequency of the second core to a second elevated operating frequency.

Abstract: Noise filtering for an incoming signal is provided. The noise filtering method includes executing a transformation operation on the incoming signal by distributing energy corresponding to each of a plurality of components of the incoming signal into a two-dimensional representation. The noise filtering method also includes executing a filtering operation on the plurality of components to determine real objects and remove noise within the incoming signal. The filtering operation utilizing at least one of a plurality of noise detection matrixes based on time, frequency, or direction.

Abstract: A generator device being configured for generating pseudo random numbers, the generator device comprising a computing device operable for (i) calculating a first hash chain from an initial hash value (H_0), the first hash chain comprising a first sequence of M hash values (HA_1, HA_2, . . . , HA_M); (ii) calculating a second hash chain (20) comprising a second sequence of M hash values (HB_1, HB_2, . . . , HB_M) from the initial hash value (H_0) and the hash values (HA_1, HA_2, . . . , HA_M) of the first sequence; and (iii) determining the pseudo random numbers from the hash values (HB_1, HB_2, . . . , HB_M) of the second sequence. Also disclosed are a method for generating pseudo random numbers and a method for quantum computing secure authentication, as well as a computer program product and a data processing system.

Abstract: Noise filtering for an incoming signal is provided. The noise filtering method includes executing a transformation operation on the incoming signal by distributing energy corresponding to each of a plurality of components of the incoming signal into a two-dimensional representation. The noise filtering method also includes executing a filtering operation on the plurality of components to determine real objects and remove noise within the incoming signal. The filtering operation utilizing at least one of a plurality of noise detection matrixes based on time, frequency, or direction.

Abstract: Secure operations are performed on encrypted code. A processor in a first operating mode obtains encrypted code. The processor switches from the first operating mode to a second operating mode, and decrypts the encrypted code to obtain decrypted code. The decrypted code is executed, based on the processor being in the second operating mode, to provide a result. The result is encrypted, and the encrypted result is sent to a user, based on the processor switching back to the first operating mode.

Abstract: Embodiments include method, systems and computer program products for compressing instrumentation data. Aspects include defining an intermediate region of memory. Instrumentation data associated with a processing device is received and stored in the intermediate region of the memory. The instrumentation data is compressed in the intermediate region of memory and stored in a sample region of memory.

Abstract: A method for distributed training in a parameter dataset; the method for at least one coordinating node; a network of at least one distributed node; receiving a parameter dataset from a first distributed node; decrypting the received dataset; training the parameter dataset based on a training data record to obtain a trained parameter dataset; and forwarding the trained parameter dataset to a second distributed node.

Abstract: Embodiments of the invention are directed to methods for improving performance of a multi-core processor. The method includes increasing a first operating frequency to a first elevated operating frequency of a first core of a gang of cores, the gang of cores comprising a plurality of cores of the multi-core processor. The method further includes upon a determination that an operating temperature of the first core is above a threshold temperature, switching processing of a thread from the first core to a second core in the gang of cores. The method further includes reducing the first operating frequency of the first core. The method further includes increasing the operating frequency of the second core to a second elevated operating frequency.

Abstract: A generator device being configured for generating pseudo random numbers, the generator device comprising a computing device operable for (i) calculating a first hash chain from an initial hash value (H_0), the first hash chain comprising a first sequence of M hash values (HA_1, HA_2, . . . , HA_M); (ii) calculating a second hash chain (20) comprising a second sequence of M hash values (HB_1, HB_2, . . . , HB_M) from the initial hash value (H_0) and the hash values (HA_1, HA_2, . . . , HA_M) of the first sequence; and (iii) determining the pseudo random numbers from the hash values (HB_1, HB_2, . . . , HB_M) of the second sequence. Also disclosed are a method for generating pseudo random numbers and a method for quantum computing secure authentication, as well as a computer program product and a data processing system.

Abstract: Embodiments relate to implementing error data collection for a processor. Aspects of the embodiments include identifying a plurality of error state devices in a processor, each of the plurality of error state devices configured to hold a state indication, and organizing the plurality of error state devices as a sequence. Aspects also include collecting a plurality of state indications by serially sampling the state indication from each of the plurality of error state devices in an order corresponding to the sequence, sequentially storing the plurality of state indications as a single linear data array, and outputting the linear data array as a data structure. The data structure can include information regarding one or more error events based on one or more errors occurring in the processor.

Abstract: Embodiments relate to implementing error data collection for a processor. Aspects of the embodiments include identifying a plurality of error state devices in a processor, each of the plurality of error state devices configured to hold a state indication, and organizing the plurality of error state devices as a sequence. Aspects also include collecting a plurality of state indications by serially sampling the state indication from each of the plurality of error state devices in an order corresponding to the sequence, sequentially storing the plurality of state indications as a single linear data array, and outputting the linear data array as a data structure. The data structure can include information regarding one or more error events based on one or more errors occurring in the processor.

Abstract: Embodiments relate to implementing error data collection for a processor. Aspects of the embodiments include identifying a plurality of error state devices in a processor, each of the plurality of error state devices configured to hold a state indication, and organizing the plurality of error state devices as a sequence. Aspects also include collecting a plurality of state indications by serially sampling the state indication from each of the plurality of error state devices in an order corresponding to the sequence, sequentially storing the plurality of state indications as a single linear data array, and outputting the linear data array as a data structure. The data structure can include information regarding one or more error events based on one or more errors occurring in the processor.

Abstract: Embodiments relate to implementing error data collection for a processor. Aspects of the embodiments include identifying a plurality of error state devices in a processor, each of the plurality of error state devices configured to hold a state indication, and organizing the plurality of error state devices as a sequence. Aspects also include collecting a plurality of state indications by serially sampling the state indication from each of the plurality of error state devices in an order corresponding to the sequence, sequentially storing the plurality of state indications as a single linear data array, and outputting the linear data array as a data structure. The data structure can include information regarding one or more error events based on one or more errors occurring in the processor.