Abstract: A method for testing packaged integrated circuits (ICs) having bent or broken leads. A lower portion of each lead is cut to leave a stub located close to the package body of the damaged IC. The damaged IC is then mounted onto a probe card having upward-facing probes that contact the lead stubs. Test signals are then transmitted between an IC tester and the damaged IC through the probe card.

Abstract: A handler interface apparatus for low-temperature semiconductor device testing that includes a bracket and a handler board. The bracket including an outer frame, an inner frame connected to the outer frame by one or more arms, and a cover plate positioned over a central opening of the inner frame. When the handler board is mounted onto the bracket, conductors extending through the handler board from a device contactor pad are enclosed in a chamber formed by the handler board, the inner frame and the cover plate. The handler board is then mated to the test pins of a device tester, which extend through openings located between the inner frame, the outer frame, and the arms of the bracket. During low temperature testing, dry gas is pumped into the chamber through conduits formed in the arms of the bracket to prevent the condensation of moisture on the conductors located in the chamber. In a second disclosed embodiment, a cover plate is attached directly to a handler board.

Abstract: An apparatus and method for testing “chip scale” integrated circuits (IC's) using a vertical probe card mounted on a printed circuit board (PCB). A nesting assembly mounted over the vertical probe card includes alignment walls and an alignment plate including chamfered through holes. The alignment walls are slanted to provide rough alignment of the IC within the nesting assembly, and fine alignment of the IC is achieved when the solder balls extending from the IC are received in the chamfers formed in the upper surface of the alignment plate. Tips of formed wire probes extend from the vertical probe card towards the bottom surface of the alignment plate. When the alignment plate is pushed towards the vertical probe card by a device handler, the tips of the wire probes extend through the through-holes and pierce the solder balls of the IC, providing electrical contact between the IC and the PCB.

Abstract: A semiconductor device tester and handler interface includes tester and handler boards with a coplanarity plate between them. The handler board includes a central area adapted to mount semiconductor devices to be tested by a tester. The tester board has tester contacts located to interface with a tester. During cold testing, to avoid condensation on the side of the handler board away from the devices being tested, dry gas is applied to the region formed by the coplanarity plate. During hot testing, flowing dry gas prevents the hot handler board from excessively heating the tester board and associated tester.

Abstract: A semiconductor device tester and handler interface includes a tester and handler board. The board includes multiple test sites and has multiple layers of metallization traces. The handler side of the board includes a central area adapted to mount multiple semiconductor devices to be tested by a tester. The tester side of the board has tester contacts located to interface with a tester. Vias connect metallization traces in one metallization layer to metallization traces in another layer. The traces and vias are arranged to form paths from a tester contact to a test socket. The test sites are placed close to and sometimes superimposed on the tester contacts receiving the test signals. Thus delay is minimized and with multiple test sites, throughput is increased.

Abstract: An interface structure for providing connections between integrated circuit (IC) devices and a device tester. The interface structure includes a printed circuit board having one or more groups of pogo pins, each group being arranged to contact the pins extending from the pin grid array package of one IC device, and includes interconnect paths from the pogo pins and the device tester. The groups of pogo pins are mounted directly into the printed circuit board in a universal footprint arrangement that is customized to receive a plurality of different pin grid array package footprints. A nonconductive cover plate is mounted over the pogo pin groups upon which the IC devices are mounted by a handler. A mother board is connected between the printed circuit board and the device tester.

Abstract: A semiconductor device tester and handler interface includes a tester mother board and a handler board. The handler board includes a central area adapted to mount multiple semiconductor devices to be tested by a tester. The tester mother board has a central area, and first and second peripheral groupings of tester contacts fixed in location on the tester mother board. A ring of spaced electrical connectors such as compressible pogo pins on the tester mother board is positioned between the first and the second groupings of tester contacts such that the area of the handler boards available for mounting semiconductor devices is enhanced. This larger area permits testing in parallel of a plurality of semiconductor devices.

Abstract: A semiconductor device tester and handler interface includes a tester mother board and a handler board. The handler board includes a central area adapted to mount multiple semiconductor devices to be tested by a tester. The tester mother board has a central area, and first and second peripheral groupings of tester contacts fixed in location on the tester mother board. A ring of spaced electrical connectors such as compressible pogo pins on the tester mother board is positioned between the first and the second groupings of tester contacts such that the area of the handler boards available for mounting semiconductor devices is enhanced. This larger area permits testing in parallel of a plurality of semiconductor devices.