Abstract: A system and method for sending and receiving data with a reliable communication protocol. The system includes a computer at a node having a backplane, a CPU board plugged into the backplane, software instructions for the CPU, and a special network board plugged into the backplane. The CPU board, software, and network card act to implement the TCP/IP protocol suite. The network card or board includes an interface to receive data packets from the physical layer, and circuitry to verify the TCP checksum before de-encapsulation and routing of the TCP segment by the network layer software. It also includes circuitry to automatically prepare the acknowledgement signal to be sent by the receiving computer to the sending computer. It additionally includes circuitry to calculate the error detecting code on outgoing signals from the sending computer to the receiving computer.

Abstract: A method and system for programming the hardware of field programmable gate arrays and related reconfigurable resources as if they were software by creating hardware objects that implement application level functionalities, operating system functionalities, and hardware functionalities. Further controlling and executing the hardware objects via high level software constructs and managing the reconfigurable resources, such that the reconfigurable resources are optimized for the tasks currently executing.

Abstract: A system and method for sending and receiving data with a reliable communication protocol. The system includes a computer at a node having a backplane, a CPU board plugged into the backplane, software instructions for the CPU, and a special network board plugged into the backplane. The CPU board, software, and network card act to implement the TCP/IP protocol suite. The network card or board includes an interface to receive data packets from the physical layer, and circuitry to verify the TCP checksum before de-encapsulation and routing of the TCP segment by the network layer software. It also includes circuitry to automatically prepare the acknowledgement signal to be sent by the receiving computer to the sending computer. It additionally includes circuitry to calculate the error detecting code on outgoing signals from the sending computer to the receiving computer.

Abstract: A programmable circuit assembly and methods for high bandwidth data processing. The assembly includes an array of in-circuit programmable logic packages interconnected with an array of memory packages, allowing for elastic buffering of data in a variety of directions. Each programmable package includes package leads, a memory, and output drivers. Each output driver is connected to a respective package lead, which is configured to generate a logic function defined by programming data stored in the memory. A method includes storing programming data for operating the assembly to send signals on different paths between a programmable package and a memory package.