Patents by Inventor Toby D. Robbs
Toby D. Robbs has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11715513Abstract: Apparatuses and methods for sense line architectures for semiconductor memories are disclosed. An example apparatus includes a first array region including first portions of a plurality of sense lines and memory cells coupled to the first portions of the plurality of sense lines and further includes a second array region including second portions of the plurality of sense lines and memory cells coupled to the second portions of the plurality of sense lines. An array gap is disposed between the first and second array regions and includes third portions of the plurality of sense lines and does not include any memory cells. Each third portion of the plurality of sense lines includes conductive structures having vertical components configured to couple the first portions and second portions of the plurality of sense lines to provide an electrically continuous sense lines through the first and second array regions and the array gap.Type: GrantFiled: January 11, 2022Date of Patent: August 1, 2023Assignee: Micron Technology, Inc.Inventors: Toby D. Robbs, Charles L. Ingalls
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Patent number: 11581035Abstract: A memory device may include a memory array having a plurality of memory cells and a first column plane having multiple column select lines. The first column select lines of the first column plane may access a first set of the memory cells associated with the first column plane. Additionally, the memory device may include a second column plane having a multiple column select lines to access a second set of the memory cells associated with the second column plane. The memory device may also include a column select line shared between the first column plane and the second column plane. The column select line may access a third set of the memory cells associated with the first column plane and a fourth set of the memory cells associated with the second column plane.Type: GrantFiled: February 24, 2021Date of Patent: February 14, 2023Assignee: Micron Technology, Inc.Inventors: Jiyun Li, Toby D. Robbs
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Publication number: 20220270668Abstract: A memory device may include a memory array having a plurality of memory cells and a first column plane having multiple column select lines. The first column select lines of the first column plane may access a first set of the memory cells associated with the first column plane. Additionally, the memory device may include a second column plane having a multiple column select lines to access a second set of the memory cells associated with the second column plane. The memory device may also include a column select line shared between the first column plane and the second column plane. The column select line may access a third set of the memory cells associated with the first column plane and a fourth set of the memory cells associated with the second column plane.Type: ApplicationFiled: February 24, 2021Publication date: August 25, 2022Inventors: Jiyun Li, Toby D. Robbs
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Publication number: 20220131003Abstract: An apparatus, such as a memory array, can have a memory cell coupled to a first digit line (e.g., a local digit line) at a first level. A second digit line (e.g., hierarchical digit line) at a second level can be coupled to a main sense amplifier. A charge sharing device at a third level between the first and second levels can be coupled to the first digit line and to a connector. A vertical transistor at the third level can be coupled between the first digit line and the connector. A contact can be coupled between the connector and the second digit line.Type: ApplicationFiled: January 4, 2022Publication date: April 28, 2022Inventors: Fatma Arzum Simsek-Ege, Steve V. Cole, Scott J. Derner, Toby D. Robbs
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Publication number: 20220130449Abstract: Apparatuses and methods for sense line architectures for semiconductor memories are disclosed. An example apparatus includes a first array region including first portions of a plurality of sense lines and memory cells coupled to the first portions of the plurality of sense lines and further includes a second array region including second portions of the plurality of sense lines and memory cells coupled to the second portions of the plurality of sense lines. An array gap is disposed between the first and second array regions and includes third portions of the plurality of sense lines and does not include any memory cells. Each third portion of the plurality of sense lines includes conductive structures having vertical components configured to couple the first portions and second portions of the plurality of sense lines to provide an electrically continuous sense lines through the first and second array regions and the array gap.Type: ApplicationFiled: January 11, 2022Publication date: April 28, 2022Applicant: MICRON TECHNOLOGY, INC.Inventors: Toby D. Robbs, Charles L. Ingalls
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Patent number: 11232829Abstract: Apparatuses and methods for sense line architectures for semiconductor memories are disclosed. An example apparatus includes a first array region including first portions of a plurality of sense lines and memory cells coupled to the first portions of the plurality of sense lines and further includes a second array region including second portions of the plurality of sense lines and memory cells coupled to the second portions of the plurality of sense lines. An array gap is disposed between the first and second array regions and includes third portions of the plurality of sense lines and does not include any memory cells. Each third portion of the plurality of sense lines includes conductive structures having vertical components configured to couple the first portions and second portions of the plurality of sense lines to provide an electrically continuous sense lines through the first and second array regions and the array gap.Type: GrantFiled: March 10, 2020Date of Patent: January 25, 2022Assignee: Micron Technology, Inc.Inventors: Toby D. Robbs, Charles L. Ingalls
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Patent number: 11222975Abstract: An apparatus, such as a memory array, can have a memory cell coupled to a first digit line (e.g., a local digit line) at a first level. A second digit line (e.g., hierarchical digit line) at a second level can be coupled to a main sense amplifier. A charge sharing device at a third level between the first and second levels can be coupled to the first digit line and to a connector. A vertical transistor at the third level can be coupled between the first digit line and the connector. A contact can be coupled between the connector and the second digit line.Type: GrantFiled: July 25, 2019Date of Patent: January 11, 2022Assignee: Micron Technology, Inc.Inventors: Fatma Arzum Simsek-Ege, Steve V. Cole, Scott J. Derner, Toby D. Robbs
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Publication number: 20210028308Abstract: An apparatus, such as a memory array, can have a memory cell coupled to a first digit line (e.g., a local digit line) at a first level. A second digit line (e.g., hierarchical digit line) at a second level can be coupled to a main sense amplifier. A charge sharing device at a third level between the first and second levels can be coupled to the first digit line and to a connector. A vertical transistor at the third level can be coupled between the first digit line and the connector. A contact can be coupled between the connector and the second digit line.Type: ApplicationFiled: July 25, 2019Publication date: January 28, 2021Inventors: Fatma Arzum Simsek-Ege, Steve V. Cole, Scott J. Derner, Toby D. Robbs
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Publication number: 20200211625Abstract: Apparatuses and methods for sense line architectures for semiconductor memories are disclosed. An example apparatus includes a first array region including first portions of a plurality of sense lines and memory cells coupled to the first portions of the plurality of sense lines and further includes a second array region including second portions of the plurality of sense lines and memory cells coupled to the second portions of the plurality of sense lines. An array gap is disposed between the first and second array regions and includes third portions of the plurality of sense lines and does not include any memory cells. Each third portion of the plurality of sense lines includes conductive structures having vertical components configured to couple the first portions and second portions of the plurality of sense lines to provide an electrically continuous sense lines through the first and second array regions and the array gap.Type: ApplicationFiled: March 10, 2020Publication date: July 2, 2020Applicant: MICRON TECHNOLOGY, INC.Inventors: Toby D. Robbs, Charles L. Ingalls
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Patent number: 10607687Abstract: Apparatuses and methods for sense line architectures for semiconductor memories are disclosed. An example apparatus includes a first array region including first portions of a plurality of sense lines and memory cells coupled to the first portions of the plurality of sense lines and further includes a second array region including second portions of the plurality of sense lines and memory cells coupled to the second portions of the plurality of sense lines. An array gap is disposed between the first and second array regions and includes third portions of the plurality of sense lines and does not include any memory cells. Each third portion of the plurality of sense lines includes conductive structures having vertical components configured to couple the first portions and second portions of the plurality of sense lines to provide an electrically continuous sense lines through the first and second array regions and the array gap.Type: GrantFiled: December 28, 2017Date of Patent: March 31, 2020Assignee: Micron Technology, Inc.Inventors: Toby D. Robbs, Charles L. Ingalls
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Patent number: 10607690Abstract: A memory device may include a memory array with multiple memory cells and one or more sense amplifiers connected to the memory array. Each sense amplifier may include a matched pair of transistors. An active matching fill feature may also be included proximate to at least one transistor of the matched pair of transistors.Type: GrantFiled: August 30, 2019Date of Patent: March 31, 2020Assignee: Micron Technology, Inc.Inventors: Steve V. Cole, Benjamin A. Millemon, Toby D. Robbs, J. W. Thompson
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Publication number: 20200075083Abstract: A memory device may include a memory array with multiple memory cells and one or more sense amplifiers connected to the memory array. Each sense amplifier may include a matched pair of transistors. An active matching fill feature may also be included proximate to at least one transistor of the matched pair of transistors.Type: ApplicationFiled: August 30, 2019Publication date: March 5, 2020Inventors: Steve V. Cole, Benjamin A. Millemon, Toby D. Robbs, J. W. Thompson
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Patent number: 10418093Abstract: A memory device may include a memory array with multiple memory cells and one or more sense amplifiers connected to the memory array. Each sense amplifier may include a matched pair of transistors. An active matching fill feature may also be included proximate to at least one transistor of the matched pair of transistors.Type: GrantFiled: August 31, 2018Date of Patent: September 17, 2019Assignee: Micron Technology, Inc.Inventors: Steve V. Cole, Benjamin A. Millemon, Toby D. Robbs, J. W. Thompson
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Publication number: 20190206480Abstract: Apparatuses and methods for sense line architectures for semiconductor memories are disclosed. An example apparatus includes a first array region including first portions of a plurality of sense lines and memory cells coupled to the first portions of the plurality of sense lines and further includes a second array region including second portions of the plurality of sense lines and memory cells coupled to the second portions of the plurality of sense lines. An array gap is disposed between the first and second array regions and includes third portions of the plurality of sense lines and does not include any memory cells. Each third portion of the plurality of sense lines includes conductive structures having vertical components configured to couple the first portions and second portions of the plurality of sense lines to provide an electrically continuous sense lines through the first and second array regions and the array gap.Type: ApplicationFiled: December 28, 2017Publication date: July 4, 2019Applicant: Micron Technology, Inc.Inventors: Toby D. Robbs, Charles L. Ingalls