Patents by Inventor Toby Opferman
Toby Opferman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240143513Abstract: An apparatus and method for switching between different types of paging using separate control registers and without disabling paging. For example, one embodiment of a processor comprises: a first control register to store a first base address of a first paging structure associated with a first type of paging having a first number of paging structure levels; a second control register to store a second base address of a second paging structure associated with a first type of paging having a second number of paging structure levels greater than the first number of paging structure levels; page walk circuitry to select either the first base address from the first control register or the second base address from the second control register responsive to a first address translation request, the selection based on a characteristic of program code initiating the address translation request.Type: ApplicationFiled: October 1, 2022Publication date: May 2, 2024Inventors: Gilbert NEIGER, Andreas KLEEN, David SHEFFIELD, Jason BRANDT, Ittai ANATI, Vedvyas SHANBHOGUE, Ido OUZIEL, Michael S. BAIR, Barry E. HUNTLEY, Joseph NUZMAN, Toby OPFERMAN, Michael A. ROTHMAN
-
Publication number: 20240126599Abstract: Systems, apparatus, articles of manufacture, and methods are disclosed to manage workloads for an operating system wherein it causes programmable circuitry to cause a task of a workload to be executed with a first processor core configuration; cause the task to be executed with a second processor core configuration; compare a first performance metric of the execution of the task with the first processor core configuration to a second performance metric of the execution with the second processor core configuration; and cause to be used one of the first processor core configuration or the second processor core configuration based on the comparison.Type: ApplicationFiled: December 26, 2023Publication date: April 18, 2024Inventors: Leslie Xu, Toby Opferman, David Bradley Sheffield, Mukta Singh
-
Patent number: 11957974Abstract: Described herein is a cloud-based gaming system in which graphics processing operations of a cloud-based game can be performed on a client device. Client-based graphics processing can be enabled in response to a determination that the client includes a graphics processor having a performance that exceeds a minimum threshold. When a game is remotely executed and streamed to a client, the client is configurable to provide network feedback that can be used to adjust execution and/or encoding for the game.Type: GrantFiled: February 5, 2021Date of Patent: April 16, 2024Assignee: Intel CorporationInventors: Makarand Dharmapurikar, Rajabali Koduri, Vijay Bahirji, Toby Opferman, Scott G. Christian, Rajeev Penmatsa, Selvakumar Panneer
-
Publication number: 20240103869Abstract: Techniques for using CPUID for showing features that are deprecated are described. In some examples, CPUID is to include at least one field for an opcode, one or more fields to identify a source operand which is to store a LSL selector value, and one or more fields to identify a destination register operand, wherein the opcode is to indicate that execution circuitry is to, when the single instruction has been enabled by a setting of a bit in a control register, write a LSL value stored in the control register to the destination operand when the LSL selector value of the first source register operand matches a LSL selector value stored in the control register, and set a flag in a flags register.Type: ApplicationFiled: September 28, 2022Publication date: March 28, 2024Inventors: Andreas Kleen, Jason Brandt, Ittai Anati, David Sheffield, Toby Opferman, Ian Hanschen, Xiang Zou, Terry Parks
-
Patent number: 11734079Abstract: The present disclosure relates to a processor that includes one or more processing elements associated with one or more instruction set architectures. The processor is configured to receive a request from an application executed by a first processing element of the one or more processing elements to enable a feature associated with an instruction set architecture. Additionally, the processor is configured to enable the application to utilize the feature without a system call occurring when the feature is associated with an instruction set architecture associated with the first processing element.Type: GrantFiled: August 5, 2022Date of Patent: August 22, 2023Assignee: Intel CorporationInventors: Toby Opferman, Eliezer Weissmann, Robert Valentine, Russell Cameron Arnold
-
Publication number: 20230091167Abstract: An embodiment of an integrated circuit may comprise an instruction decoder to decode one or more instructions to be executed by a core, and circuitry coupled to the instruction decoder, the circuitry to determine if a decoded instruction involves a page to be fetched, and determine one or more hints for one or more optional pages that may be fetched along with the page for the decoded instruction. Other embodiments are disclosed and claimed.Type: ApplicationFiled: September 23, 2021Publication date: March 23, 2023Applicant: Intel CorporationInventors: Toby Opferman, Michael W. Chynoweth, Rajshree A. Chabukswar, Vijay C. Bahirji
-
Publication number: 20220374278Abstract: The present disclosure relates to a processor that includes one or more processing elements associated with one or more instruction set architectures. The processor is configured to receive a request from an application executed by a first processing element of the one or more processing elements to enable a feature associated with an instruction set architecture. Additionally, the processor is configured to enable the application to utilize the feature without a system call occurring when the feature is associated with an instruction set architecture associated with the first processing element.Type: ApplicationFiled: August 5, 2022Publication date: November 24, 2022Inventors: Toby Opferman, Eliezer Weissmann, Robert Valentine, Russell Cameron Arnold
-
Patent number: 11507368Abstract: Embodiments of processors, methods, and systems for a processor core supporting processor identification instruction spoofing are described. In an embodiment, a processor includes an instruction decoder and processor identification instruction spoofing logic. The processor identification spoofing logic is to respond to a processor identification instruction by reporting processor identification information from a processor identification spoofing data structure. The processor identification spoofing data structure is to include processor identification information of one or more other processors.Type: GrantFiled: December 25, 2020Date of Patent: November 22, 2022Assignee: Intel CorporationInventors: Toby Opferman, Russell C. Arnold, Vedvyas Shanbhogue
-
Patent number: 11461098Abstract: Systems, methods, and apparatuses relating to an instruction for operating system transparent instruction state management of new instructions for application threads are described. In one embodiment, a hardware processor includes a decoder to decode a single instruction into a decoded single instruction, and an execution circuit to execute the decoded single instruction to cause a context switch from a current state to a state comprising additional state data that is not supported by an execution environment of an operating system that executes on the hardware processor.Type: GrantFiled: June 27, 2020Date of Patent: October 4, 2022Assignee: Intel CorporationInventors: Toby Opferman, Prashant Sethi, Abhimanyu K. Varde, Barry E. Huntley, Michael W. Chynoweth, Jason W. Brandt
-
Publication number: 20220262427Abstract: A mechanism where the locked pages are saved and restored by a hardware accelerator which is transparent to the OS. Prior to standby entry, the OS puts all DMA capable devices in the lowest-powered device low-power state after disabling bus mastering. The OS flushes all pageable memory to an NVM (in segments that are kept in self-refresh) and provides a list of pinned and locked pages in the DRAM to a power management controller (p-unit). The p-unit checks for all Bus Mastering DMA to be turned off and checks if a next OS timer wake event (TNTE) is greater than a threshold, to decide whether to enable or disable PASR or MPSM in Standby. If the conditions are met, the p-unit triggers a hardware accelerator to consolidate the pinned and locked pages in the DRAM to certain segment(s) of the DRAM during standby states, making it transparent to the OS.Type: ApplicationFiled: February 17, 2021Publication date: August 18, 2022Applicant: Intel CorporationInventors: Nivedha Krishnakumar, Virendra Vikramsinh Adsure, Jaya Jeyaseelan, Nadav Bonen, Barnes Cooper, Toby Opferman, Vijay Bahirji, Chia-Hung Kuo
-
Patent number: 11409572Abstract: The present disclosure relates to a processor that includes one or more processing elements associated with one or more instruction set architectures. The processor is configured to receive a request from an application executed by a first processing element of the one or more processing elements to enable a feature associated with an instruction set architecture. Additionally, the processor is configured to enable the application to utilize the feature without a system call occurring when the feature is associated with an instruction set architecture associated with the first processing element.Type: GrantFiled: September 27, 2019Date of Patent: August 9, 2022Assignee: Intel CorporationInventors: Toby Opferman, Eliezer Weissmann, Robert Valentine, Russell Cameron Arnold
-
Publication number: 20210406019Abstract: Systems, methods, and apparatuses relating to an instruction for operating system transparent instruction state management of new instructions for application threads are described. In one embodiment, a hardware processor includes a decoder to decode a single instruction into a decoded single instruction, and an execution circuit to execute the decoded single instruction to cause a context switch from a current state to a state comprising additional state data that is not supported by an execution environment of an operating system that executes on the hardware processor.Type: ApplicationFiled: June 27, 2020Publication date: December 30, 2021Inventors: TOBY OPFERMAN, PRASHANT SETHI, ABHIMANYU K. VARDE, BARRY E. HUNTLEY, MICHAEL W. Chynoweth, JASON W. BRANDT
-
Publication number: 20210342213Abstract: A processing device is provided. The processing device comprises an interface configured to receive information about an operation state of a surrogate processor. Further, the processing device comprises a processing circuitry configured to decide whether an interrupt addressed to the processing circuitry is processed by the processing circuitry or redirected to the surrogate processing circuitry based on an operation state of the processing circuitry and the surrogate processing circuitry.Type: ApplicationFiled: July 14, 2021Publication date: November 4, 2021Inventors: Karunakara KOTARY, Toby OPFERMAN, Deepak GANDIGA SHIVAKUMAR, Vijay C. BAHIRJI, Rajesh POORNACHANDRAN
-
Publication number: 20210245046Abstract: Described herein is a cloud-based gaming system in which graphics processing operations of a cloud-based game can be performed on a client device. Client-based graphics processing can be enabled in response to a determination that the client includes a graphics processor having a performance that exceeds a minimum threshold. When a game is remotely executed and streamed to a client, the client is configurable to provide network feedback that can be used to adjust execution and/or encoding for the game.Type: ApplicationFiled: February 5, 2021Publication date: August 12, 2021Applicant: Intel CorporationInventors: MAKARAND DHARMAPURIKAR, RAJABALI KODURI, VIJAY BAHIRJI, TOBY OPFERMAN, SCOTT G. CHRISTIAN, RAJEEV PENMATSA, SELVAKUMAR PANNEER
-
Patent number: 11055094Abstract: Disclosed embodiments relate to improved heterogeneous CPUID spoofing for remote processors. In one example, a system includes multiple processors, including a first processor including configuration circuitry to enable remote processor identification (ID) spoofing; fetch circuitry to fetch an instruction; decode circuitry to decode the instruction having fields to specify an opcode and a context, the opcode indicating execution circuitry is to: when remote processor ID spoofing is enabled, access a processor ID spoofing data structure storing processor ID information for each of the plurality of processors, and report processor ID information for a processor identified by the context; and, when remote processor ID spoofing is not enabled, report processor ID information for the first processor; and execution circuitry to execute the instruction as per the opcode.Type: GrantFiled: June 26, 2019Date of Patent: July 6, 2021Assignee: Intel CorporationInventors: Toby Opferman, Russell C. Arnold, Vedvyas Shanbhogue, Michael W. Chynoweth
-
Publication number: 20210117190Abstract: Embodiments of processors, methods, and systems for a processor core supporting processor identification instruction spoofing are described. In an embodiment, a processor includes an instruction decoder and processor identification instruction spoofing logic. The processor identification spoofing logic is to respond to a processor identification instruction by reporting processor identification information from a processor identification spoofing data structure. The processor identification spoofing data structure is to include processor identification information of one or more other processors.Type: ApplicationFiled: December 25, 2020Publication date: April 22, 2021Applicant: Intel CorporationInventors: Toby Opferman, Russell C. Arnold, Vedvyas Shanbhogue
-
Publication number: 20210096908Abstract: The present disclosure relates to a processor that includes one or more processing elements associated with one or more instruction set architectures. The processor is configured to receive a request from an application executed by a first processing element of the one or more processing elements to enable a feature associated with an instruction set architecture. Additionally, the processor is configured to enable the application to utilize the feature without a system call occurring when the feature is associated with an instruction set architecture associated with the first processing element.Type: ApplicationFiled: September 27, 2019Publication date: April 1, 2021Inventors: Toby Opferman, Eliezer Weissmann, Robert Valentine, Russell Cameron Arnold
-
Patent number: 10949207Abstract: Embodiments of processors, methods, and systems for a processor core supporting a heterogenous system instruction set architecture are described. In an embodiment, a processor includes an instruction decoder and an exception generation circuit. The exception generation circuit is to, in response to the instruction decoder receiving an unsupported instruction, generate an exception and report an instruction classification value of the unsupported instruction.Type: GrantFiled: September 29, 2018Date of Patent: March 16, 2021Assignee: Intel CorporationInventors: Toby Opferman, Russell C. Arnold, Vedvyas Shanbhogue
-
Publication number: 20210019260Abstract: Systems, apparatuses and methods may provide for technology that identifies a NUMA node, defines a first virtual proximity domain within the NUMA node, and defines a second virtual proximity domain within the NUMA node, wherein the first virtual proximity domain and the second virtual proximity domain are defined via one or more OS interface tables.Type: ApplicationFiled: August 6, 2020Publication date: January 21, 2021Inventors: Kyle Delehanty, Sridharan Sakthivelu, Janardhana Yoga Narasimhaswamy, Vijay Bahirji, Toby Opferman
-
Publication number: 20200409708Abstract: Disclosed embodiments relate to improved heterogeneous CPUID spoofing for remote processors. In one example, a system includes multiple processors, including a first processor including configuration circuitry to enable remote processor identification (ID) spoofing; fetch circuitry to fetch an instruction; decode circuitry to decode the instruction having fields to specify an opcode and a context, the opcode indicating execution circuitry is to: when remote processor ID spoofing is enabled, access a processor ID spoofing data structure storing processor ID information for each of the plurality of processors, and report processor ID information for a processor identified by the context; and, when remote processor ID spoofing is not enabled, report processor ID information for the first processor; and execution circuitry to execute the instruction as per the opcode.Type: ApplicationFiled: June 26, 2019Publication date: December 31, 2020Applicant: Intel CorporationInventors: Toby OPFERMAN, Russell C. ARNOLD, Vedvyas SHANBHOGUE, Michael W. CHYNOWETH