Abstract: A radio-frequency (RF) receiver includes a receiver analog circuitry and a receiver digital circuitry. The receiver analog circuitry resides within a first integrated circuit and the receiver digital circuitry resides within a second integrated circuit. The second integrated circuit couples to the first integrated circuit via a one-bit digital interface. The receiver analog circuitry receives an RF signal and processes the received RF signal to generate a digital signal. The receiver analog circuitry provides the digital signal to the receiver digital circuitry. The receiver digital circuitry includes a digital down-converter circuitry that mixes the digital signal with an intermediate frequency (IF) local oscillator (LO) signal to generate a digital down-converted signal. The receiver digital circuitry also includes a digital filter circuitry that filters the digital down-converted signal to generate a filtered digital signal.

Abstract: A method is disclosed for performing dual mode image rejection calibration in a receiver. A first image correction factor is acquired using a first known signal associated with a first signal band during a startup mode. The first image correction factor has a plurality of bits including most significant bits (MSBs) and least significant bits (LSBs). The LSBs of the first image correction factor are adjusted incrementally during a normal operation mode. A radio frequency (RF) signal associated with the first signal band is received using the first image correction factor during the normal operation mode.

Abstract: A method is disclosed for performing dual mode image rejection calibration in a receiver. A first image correction factor is acquired using a first known signal associated with a first signal band during a startup mode. The first image correction factor has a plurality of bits including most significant bits (MSBs) and least significant bits (LSBs). The LSBs of the first image correction factor are adjusted incrementally during a normal operation mode. A radio frequency (RF) signal associated with the first signal band is received using the first image correction factor during the normal operation mode.

Abstract: A radio-frequency (RF) receiver includes a receiver analog circuitry and a receiver digital circuitry. The receiver analog circuitry resides within a first integrated circuit and the receiver digital circuitry resides within a second integrated circuit. The second integrated circuit couples to the first integrated circuit via a one-bit digital interface. The receiver analog circuitry receives an RF signal and processes the received RF signal to generate a digital signal. The receiver analog circuitry provides the digital signal to the receiver digital circuitry. The receiver digital circuitry includes a digital down-converter circuitry that mixes the digital signal with an intermediate frequency (IF) local oscillator (LO) signal to generate a digital down-converted signal. The receiver digital circuitry also includes a digital filter circuitry that filters the digital down-converted signal to generate a filtered digital signal.

Abstract: A radio-frequency (RF) receiver includes a receiver analog circuitry and a receiver digital circuitry. The receiver analog circuitry resides within a first integrated circuit and the receiver digital circuitry resides within a second integrated circuit. The second integrated circuit couples to the first integrated circuit via a one-bit digital interface. The receiver analog circuitry receives an RF signal and processes the received RF signal to generate a digital signal. The receiver analog circuitry provides the digital signal to the receiver digital circuitry. The receiver digital circuitry includes a digital down-converter circuitry that mixes the digital signal with an intermediate frequency (IF) local oscillator (LO) signal to generate a digital down-converted signal. The receiver digital circuitry also includes a digital filter circuitry that filters the digital down-converted signal to generate a filtered digital signal.

Abstract: A method is disclosed for performing dual mode image rejection calibration in a receiver. A first image correction factor is acquired for use in a receiver system using a first known signal associated with a first signal band during a startup mode. The first image correction factor is adjusted incrementally during a normal operation mode. A radio frequency (RF) signal associated with the first signal band is received using the first image correction factor during the normal operation mode.

Abstract: An apparatus and method for performing digital image correction in a receiver. In one embodiment, a receiver circuit may include an IQ signal source configured to provide a digital signal comprising in-phase (I) and quadrature (Q) components, such as an IQ mixer in combination with an analog to digital converter, for example. The receiver circuit may also include an image correction unit coupled to the IQ signal source and configured to combine the digital signal with a complex image correction factor. The image correction unit may be implemented using a digital signal processor under the control of associated program instructions, for example. In one specific implementation of the receiver circuit, the image correction unit may be configured to combine the digital signal with the complex image correction factor using a cross-accumulation operation.

Abstract: A wireless communication receiver is disclosed that operates in a test mode to determine image correction information that is used to suppress undesired image signals when the receiver switches to a normal operational mode. In one embodiment, the receiver includes a frequency synthesizer coupled by a quadrature divider to an in-phase (I) mixer and a quadrature mixer. The mixers are coupled by respective analog to digital converters (ADCs) to respective I and Q channel inputs of a digital signal processor (DSP). In the test mode, a test tone is provided to the mixer inputs. The test tone is divided down further and provided to clock the frequency synthesizer, the ADCs and the DSP. This configuration locks together the mixers, frequency synthesizer, ADCs and DSP ratiometrically in frequency during the test mode while image correction information is being determined.

Abstract: Components of a radio-frequency (RF) apparatus including transceiver circuitry and frequency modification circuitry of a crystal oscillator circuit that generates a reference signal with adjustable frequency may be partitioned in a variety of ways, for example, as one or more separate integrated circuits. The frequency modification circuitry may be implemented as part of a crystal oscillator circuit that includes digitally controlled crystal oscillator (“DCXO”) circuitry and a crystal. The frequency modification circuitry may include at least one variable capacitance device and may be employed to generate a reference signal with adjustable frequency. The adjustable reference signal may be provided to other components of the RF apparatus and/or the RF apparatus may be configured to provide the adjustable reference signal to baseband processor circuitry.

Abstract: A radio-frequency receiver circuitry includes a down-converter circuitry, an analog-to-digital converter circuitry, and a DC offset reduction circuitry. The down-converter circuitry accepts a received radio-frequency signal and processes the radio-frequency signal to provide an in-phase down-converted signal and a quadrature down-converted signal to the analog-to-digital converter circuitry. The analog-to-digital converter circuitry converts the in-phase and quadrature down-converted signals to an in-phase digital output signal and a quadrature digital output signal, respectively. The DC offset reduction circuitry couples to the analog-to-digital converter circuitry, and tends to reduce a DC offset transmitted to the in-phase and quadrature digital output signals.

Abstract: Components of a radio-frequency (RF) apparatus including transceiver circuitry and frequency modification circuitry of a crystal oscillator circuit that generates a reference signal with adjustable frequency may be partitioned in a variety of ways, for example, as one or more separate integrated circuits. The frequency modification circuitry may be implemented as part of a crystal oscillator circuit that includes digitally controlled crystal oscillator (“DCXO”) circuitry and a crystal. The frequency modification circuitry may include at least one variable capacitance device and may be employed to generate a reference signal with adjustable frequency. The adjustable reference signal may be provided to other components of the RF apparatus and/or the RF apparatus may be configured to provide the adjustable reference signal to baseband processor circuitry.

Abstract: Components of a radio-frequency (RF) apparatus including transceiver circuitry and frequency modification circuitry of a crystal oscillator circuit that generates a reference signal with adjustable frequency may be partitioned in a variety of ways, for example, as one or more separate integrated circuits. The frequency modification circuitry may be implemented as part of a crystal oscillator circuit that includes digitally controlled crystal oscillator (“DCXO”) circuitry and a crystal. The frequency modification circuitry may include at least one variable capacitance device and may be employed to generate a reference signal with adjustable frequency. The adjustable reference signal may be provided to other components of the RF apparatus and/or the RF apparatus may be configured to provide the adjustable reference signal to baseband processor circuitry.

Abstract: An apparatus and method for deriving a digital image correction factor in a receiver. In one embodiment, a receiver circuit may include an error detection circuit configured to receive a digital signal comprising in-phase (I) and quadrature (Q) components and to detect an error in a complex image correction factor, and an error correction circuit coupled to the error detection circuit and configured to modify the complex image correction factor dependent upon the detected error. In one specific implementation of the receiver circuit, the error detection circuit and the error correction circuit may be coupled in a feedback loop, where the error detection circuit may be configured to iteratively detect the error in the complex image correction factor, and where the error correction circuit may be configured to iteratively correct the error.

Abstract: An apparatus and method for performing digital image correction in a receiver. In one embodiment, a receiver circuit may include an IQ signal source configured to provide a digital signal comprising in-phase (I) and quadrature (Q) components, such as an IQ mixer in combination with an analog to digital converter, for example. The receiver circuit may also include an image correction unit coupled to the IQ signal source and configured to combine the digital signal with a complex image correction factor. The image correction unit may be implemented using a digital signal processor under the control of associated program instructions, for example. In one specific implementation of the receiver circuit, the image correction unit may be configured to combine the digital signal with the complex image correction factor using a cross-accumulation operation.

Abstract: An apparatus and method for performing digital image correction in a receiver. In one embodiment, a receiver circuit may include an IQ signal source configured to provide a digital signal comprising in-phase (I) and quadrature (Q) components, such as an IQ mixer in combination with an analog to digital converter, for example. The receiver circuit may also include an image correction unit coupled to the IQ signal source and configured to combine the digital signal with a complex image correction factor. The image correction unit may be implemented using a digital signal processor under the control of associated program instructions, for example. In one specific implementation of the receiver circuit, the image correction unit may be configured to combine the digital signal with the complex image correction factor using a cross-accumulation operation.

Abstract: A radio-frequency (RF) receiver includes a receiver analog circuitry and a receiver digital circuitry. The receiver analog circuitry resides within a first integrated circuit and the receiver digital circuitry resides within a second integrated circuit. The second integrated circuit couples to the first integrated circuit via a one-bit digital interface. The receiver analog circuitry receives an RF signal and processes the received RF signal to generate a digital signal. The receiver analog circuitry provides the digital signal to the receiver digital circuitry. The receiver digital circuitry includes a digital down-converter circuitry that mixes the digital signal with an intermediate frequency (IF) local oscillator (LO) signal to generate a digital down-converted signal. The receiver digital circuitry also includes a digital filter circuitry that filters the digital down-converted signal to generate a filtered digital signal.

Abstract: A method is disclosed for performing dual mode image rejection calibration in a receiver. A first image correction factor is acquired (1302) for use in a receiver system (15) using a first known signal associated with a first signal band during a startup mode. The first image correction factor is adjusted incrementally (1310) during a normal operation mode. A radio frequency (RF) signal associated with the first signal band is received (1324) using the first image correction factor during the normal operation mode.

Abstract: A wireless communication receiver is disclosed that operates in a test mode to determine image correction information that is used to suppress undesired image signals when the receiver switches to a normal operational mode. In one embodiment, the receiver includes a frequency synthesizer coupled by a quadrature divider to an in-phase (I) mixer and a quadrature mixer. The mixers are coupled by respective analog to digital converters (ADCs) to respective I and Q channel inputs of a digital signal processor (DSP). In the test mode, a test tone is provided to the mixer inputs. The test tone is divided down further and provided to clock the frequency synthesizer, the ADCs and the DSP. This configuration locks together the mixers, frequency synthesizer, ADCs and DSP ratiometrically in frequency during the test mode while image correction information is being determined.

Abstract: A radio-frequency (RF) receiver includes a receiver analog circuitry and a receiver digital circuitry coupled together. The receiver analog circuitry receives an RF signal. The receiver analog circuitry processes the received RF signal and generates a digital signal that it provides to the receiver digital circuitry. The receiver digital circuitry includes a digital down-converter circuitry that mixes the digital signal provided by a receiver analog circuitry with a digital intermediate frequency (IF) local oscillator signal to generate a digital down-converted signal. The receiver digital circuitry also includes a digital filter circuitry that filters the digital down-converted signal to generate a filtered digital signal. The digital filter circuitry provides a notch at a frequency that corresponds to a residual DC offset of the receiver analog circuitry.

Abstract: A radio-frequency (RF) receiver includes a receiver analog circuitry and a receiver digital circuitry. The receiver analog circuitry resides within a first integrated circuit and the receiver digital circuitry resides within a second integrated circuit. The second integrated circuit couples to the first integrated circuit via a one-bit digital interface. The receiver analog circuitry receives an RF signal and processes the received RF signal to generate a digital signal. The receiver analog circuitry provides the digital signal to the receiver digital circuitry. The receiver digital circuitry includes a digital down-converter circuitry that mixes the digital signal with an intermediate frequency (IF) local oscillator (LO) signal to generate a digital down-converted signal. The receiver digital circuitry also includes a digital filter circuitry that filters the digital down-converted signal to generate a filtered digital signal.