Abstract: A gun having at least two barrels wherein each barrel is adapted to receive at least one projectile. The barrels are attached to a gun body having a gun chamber adapted to receive a propelling charge. An interface between the gun chamber and the barrels selectively connects the gun chamber with one or more of the barrels to fire a variable number of projectiles at variable velocities.

Abstract: A method and apparatus for heterogeneous chip multiprocessors (CMP) via resource restriction. In one embodiment, the method includes the accessing of a resource utilization register to identify a resource utilization policy. Once accessed, a processor controller ensures that the processor core utilizes a shared resource in a manner specified by the resource utilization policy. In one embodiment, each processor core within a CMP includes an instruction issue throttle resource utilization register, an instruction fetch throttle resource utilization register and other like ways of restricting its utilization of shared resources within a minimum and maximum utilization level. In one embodiment, resource restriction provides a flexible manner for allocating current and power resources to processor cores of a CMP that can be controlled by hardware or software. Other embodiments are described and claimed.

Abstract: A method and apparatus for heterogeneous chip multiprocessors (CMP) via resource restriction. In one embodiment, the method includes the accessing of a resource utilization register to identify a resource utilization policy. Once accessed, a processor controller ensures that the processor core utilizes a shared resource in a manner specified by the resource utilization policy. In one embodiment, each processor core within a CMP includes an instruction issue throttle resource utilization register, an instruction fetch throttle resource utilization register and other like ways of restricting its utilization of shared resources within a minimum and maximum utilization level. In one embodiment, resource restriction provides a flexible manner for allocating current and power resources to processor cores of a CMP that can be controlled by hardware or software. Other embodiments are described and claimed.

Abstract: A method and apparatus for heterogeneous chip multiprocessors (CMP) via resource restriction. In one embodiment, the method includes the accessing of a resource utilization register to identify a resource utilization policy. Once accessed, a processor controller ensures that the processor core utilizes a shared resource in a manner specified by the resource utilization policy. In one embodiment, each processor core within a CMP includes an instruction issue throttle resource utilization register, an instruction fetch throttle resource utilization register and other like ways of restricting its utilization of shared resources within a minimum and maximum utilization level. In one embodiment, resource restriction provides a flexible manner for allocating current and power resources to processor cores of a CMP that can be controlled by hardware or software. Other embodiments are described and claimed.

Abstract: A tracheostomy tube for use with a neck plate having an aperture. The tracheostomy tube comprises an elongate outer cannula having a lumen and configured to extend through the aperture; an elongate inner cannula having a lumen and an inflatable cuff, and configured to extend through the lumen of the outer cannula such that the cuff extends beyond a distal end of the outer cannula; and an interlocking mechanism configured to releasably secure a proximal end of the inner cannula to a proximal end of the outer cannula.

Abstract: The present invention relates to electrical wiring components, and more particularly, to an electrical utility box having a mechanism for providing vertical adjustment after attachment to a wall stud, both before and after wall surface installation and during all phases of construction. A first preferred embodiment of the present invention includes an electrical utility box attached to a mounting bracket containing a slot placed longitudinally along the center of the bracket, thereby allowing the electrical utility box to slide along the length of the bracket. A second preferred embodiment includes an electrical utility box and a T-shaped mounting bracket permanently fixed to the electrical box, thereby allowing the combination to be used as a conventional electrical utility box assembly. In addition, an L-shaped optional adjustable mounting bracket to provides a vertical adjustment capability when combined with a T-shaped mounting bracket.

Abstract: A system, apparatus, and method for a core rationing logic to enable cores of a multi-core processor to adhere to various power and thermal constraints.

Abstract: A method and apparatus for global and local power management is herein described. Hardware within monitor/receives power management requests for any number of processing elements and adjusts global performance resources to change the global power state of all the processing elements or adjusts a local performance resource for a processing element to operate that processing element at a pseudo power state within the global power state.

Abstract: A system, apparatus, and method for a core rationing logic to enable cores of a multi-core processor to adhere to various power and thermal constraints.

Abstract: A system, apparatus, and method for a core rationing logic to enable cores of a multi-core processor to adhere to various power and thermal constraints.

Abstract: A mechanism for P-state feedback to operating system (OS) with hardware coordination is described herein. In one embodiment, an example of a process includes, but is not limited to, receiving data from a processor representing an average performance over a previous period of time, and determining a performance state (P-state) for a next period of time based in part on the data representing the average performance over the previous period of time. Other methods and apparatuses are also described.

Abstract: A system, apparatus, and method for a core rationing logic to enable cores of a multi-core processor to adhere to various power and thermal constraints.

Abstract: A system, apparatus, and method for a core rationing logic to enable cores of a multi-core processor to adhere to various power and thermal constraints.

Abstract: A system, apparatus, and method for a core rationing logic to enable cores of a multi-core processor to adhere to various power and thermal constraints.

Abstract: A system, apparatus, and method for a core rationing logic to enable cores of a multi-core processor to adhere to various power and thermal constraints.

Abstract: A system, apparatus, and method for a core rationing logic to enable cores of a multi-core processor to adhere to various power and thermal constraints.

Abstract: A method and apparatus for global and local power management is herein described. Hardware within monitor/receives power management requests for any number of processing elements and adjusts global performance resources to change the global power state of all the processing elements or adjusts a local performance resource for a processing element to operate that processing element at a pseudo power state within the global power state.

Abstract: A method and apparatus for heterogeneous chip multiprocessors (CMP) via resource restriction. In one embodiment, the method includes the accessing of a resource utilization register to identify a resource utilization policy. Once accessed, a processor controller ensures that the processor core utilizes a shared resource in a manner specified by the resource utilization policy. In one embodiment, each processor core within a CMP includes an instruction issue throttle resource utilization register, an instruction fetch throttle resource utilization register and other like ways of restricting its utilization of shared resources within a minimum and maximum utilization level. In one embodiment, resource restriction provides a flexible manner for allocating current and power resources to processor cores of a CMP that can be controlled by hardware or software. Other embodiments are described and claimed.

Abstract: A mechanism for P-state feedback to operating system (OS) with hardware coordination is described herein. In one embodiment, an example of a process includes, but is not limited to, receiving data from a processor representing an average performance over a pervious period of time, and determining a performance state (P-state) for a next period of time based in part on the data representing the average performance over the previous period of time. Other methods and apparatuses are also described.

Abstract: A system, apparatus, and method for a core rationing logic to enable cores of a multi-core processor to adhere to various power and thermal constraints.