Abstract: A method, apparatus, system, and signal-bearing medium that, in an embodiment, detect a new task priority for a processor, where the processor is connected to a first node, find a home node for the processor via a cluster to which the processor belongs, and send the new task priority to the home node if the home node is different from the first node. In another embodiment, an interrupt directed to a first processor is detected, the interrupt is determined to be redirectable, a home node for the first process is found via a cluster to which the first processor belongs, and an interrupt vector is sent to the home node if the home node is different from the first node.

Abstract: A method of modifying an integrated circuit design. A noise threshold is determined. A threshold, noisy wire length for a particular integrated circuit design is selected. An integrated circuit design is examined for problem networks or wires and all branches that cumulatively equal or exceed the designated threshold noisy wire length. Once the problem networks are identified, the driver circuits driving the problem networks are temporarily replaced with driver circuits with lesser driving capacity. The integrated circuit design is then tested and any new timing failures are identified. Networks that include new timing failures are isolated with symmetric and/or asymmetric wire configurations. This method of modifying an integrated circuit design is non-intrusive to existing neighboring wires, and thus the timing in existing wires is preserved.

Abstract: A method and a virtual port register array are provided for implementing shared access to a register array port by multiple sources simultaneously. A plurality of write data stages is provided for transferring write data to a plurality of register arrays from the multiple sources. A plurality of read data stages is provided for transferring read data from the plurality of register arrays to the multiple sources. A respective multiplexer stage is coupled between the write data stages and the physical write port and the read data stages and the physical read port and clocking is provided to alternate register array access and to allow pass-through of only one source request at a time per physical write port and physical read port.