Abstract: A system includes a processor, such as a CPU, surrounded by high-density memory with lower profile than a standard DIMM. The low profile, high-density memory provides multiple memory channels for the processor. With the memory configuration, the system can maintain the memory configurability with increased density and increased memory channels for the processor.

Abstract: Four-way pseudo split Dynamic Random Access Memory (DRAM) architectures and techniques are described. In one example, a 4-way pseudo split DRAM device includes four slices. In one example, a memory channel includes four pseudo channels, each of the four pseudo channels includes a corresponding slice of each of the plurality of DRAM devices. In one example, each of the four pseudo channels includes one slice from each of the plurality of DRAM devices.

Abstract: Bandwidth efficiency is improved by reducing time to access a cache line in a DRAM chip. A memory array in the DRAM chip is internally segmented into two equal size portions, each portion having a plurality of banks. Each respective portion is internally segmented into two equal size sub-portions. A cache line in the memory array is accessed by accessing a first half of the cache line in parallel in all of the sub-portions and accessing a second half of the cache line in parallel in all of the sub-portions of the memory array after a gap time.

Abstract: Techniques for storing and accessing metadata within selective dynamic random access memory (DRAM) devices are described. In one example, a dual in-line memory module (DIMM) includes a plurality of dynamic random access memory (DRAM) devices, wherein each of plurality of DRAM devices includes on-die ECC bits. At least one of the plurality of DRAM devices includes circuitry to provide access to read from and write to the on-die ECC bits of the DRAM device. The DIMM includes one or more pins to transmit metadata to and from the on-die ECC bits of the DRAM device.

Abstract: Methods and apparatus for Cross DRAM DIMM sub-channel pairing. Memory channels on a memory controller or System on a Chip (SoC) are segmented into two subchannels, each including Command and Address (C/A) signals, DQ (data) lines. Under different solutions the two subchannels may share a command-bus clock or use separate command-bus clocks. Some approaches use subchannels from different memory channels to provide the C/A and DQ lines for two subchannels to a given DIMM. One solution implements an additional command-bus clock on the DIMM connector repurposing existing MCR pins to provide command-bus clock signals to a Registered Clock Driver (RCD) to allow the subchannels to be fully independent. Another solution is the pair every other DRAM controller to the same command-bus clock. Other solutions employ Skip-1, Skip-2, and Skip-3 configurations under which the clocks for the DDR-IO circuitry are not logically co-located with the subchannel IO circuitry.

Abstract: In an example, a system and method for centering in a high-performance interconnect (HPI) are disclosed. When an interconnect is powered up from a dormant state, it may be necessary to “center” the clock signal to ensure that data are read at the correct time. A multi-phase method may be used, in which a first phase comprises a reference voltage sweep to identify an optimal reference voltage. A second phase comprises a phase sweep to identify an optimal phase. A third sweep comprises a two-dimensional “eye” phase, in which a plurality of values within a two-dimensional eye derived from the first two sweeps are tested. In each case, the optimal value is the value that results in the fewest bit error across multiple lanes. In one example, the second and third phases are performed in software, and may include testing a “victim” lane, with adjacent “aggressor” lanes having a complementary bit pattern.

Abstract: In an example, a system and method for centering in a high-performance interconnect (HPI) are disclosed. When an interconnect is powered up from a dormant state, it may be necessary to “center” the clock signal to ensure that data are read at the correct time. A multi-phase method may be used, in which a first phase comprises a reference voltage sweep to identify an optimal reference voltage. A second phase comprises a phase sweep to identify an optimal phase. A third sweep comprises a two-dimensional “eye” phase, in which a plurality of values within a two-dimensional eye derived from the first two sweeps are tested. In each case, the optimal value is the value that results in the fewest bit error across multiple lanes. In one example, the second and third phases are performed in software, and may include testing a “victim” lane, with adjacent “aggressor” lanes having a complementary bit pattern.

Abstract: In an example, a system and method for centering in a high-performance interconnect (HPI) are disclosed. When an interconnect is powered up from a dormant state, it may be necessary to “center” the clock signal to ensure that data are read at the correct time. A multi-phase method may be used, in which a first phase comprises a reference voltage sweep to identify an optimal reference voltage. A second phase comprises a phase sweep to identify an optimal phase. A third sweep comprises a two-dimensional “eye” phase, in which a plurality of values within a two-dimensional eye derived from the first two sweeps are tested. In each case, the optimal value is the value that results in the fewest bit error across multiple lanes. In one example, the second and third phases are performed in software, and may include testing a “victim” lane, with adjacent “aggressor” lanes having a complementary bit pattern.

Abstract: An electronic device for transmitting data is described herein. In some examples, the electronic device includes a package substrate, and a plurality of integrated circuits to be coupled to the package substrate, at least one integrated circuit comprising a topside connector or an edge connector to be coupled to a cable that is to couple to a cable receptacle.

Abstract: Apparatuses for interconnecting integrated circuit dies. A first set of single-ended transmitter circuits are included on a first die. The transmitter circuits are impedance matched and have no equalization. A first set of single-ended receiver circuits are included on a second die. The receiver circuits have no termination and no equalization. Conductive lines are coupled between the first set of transmitter circuits and the first set of receiver circuits. The lengths of the conductive lines are matched. The first die, the first set of single-ended transmitter circuits, the second die, the first set of single ended receiver circuits and the conductive lines are disposed within a first package. A second set of single-ended transmitter circuits are included on the first die. The transmitter circuits are impedance matched and have no equalization. Data transmitted from the second set of transmitter circuits is transmitted according to a data bus inversion (DBI) scheme.

Abstract: An on-package interface. A first set of single-ended transmitter circuits on a first die. The transmitter circuits are impedance matched and have no equalization. A first set of single-ended receiver circuits on a second die. The receiver circuits have no termination and no equalization. A plurality of conductive lines couple the first set of transmitter circuits and the first set of receiver circuits. The lengths of the plurality of conductive lines are matched.

Abstract: In an example, a system and method for centering in a high-performance interconnect (HPI) are disclosed. When an interconnect is powered up from a dormant state, it may be necessary to “center” the clock signal to ensure that data are read at the correct time. A multi-phase method may be used, in which a first phase comprises a reference voltage sweep to identify an optimal reference voltage. A second phase comprises a phase sweep to identify an optimal phase. A third sweep comprises a two-dimensional “eye” phase, in which a plurality of values within a two-dimensional eye derived from the first two sweeps are tested. In each case, the optimal value is the value that results in the fewest bit error across multiple lanes. In one example, the second and third phases are performed in software, and may include testing a “victim” lane, with adjacent “aggressor” lanes having a complementary bit pattern.

Abstract: An electronic device for transmitting data is described herein. In some examples, the electronic device includes a package substrate, and a plurality of integrated circuits to be coupled to the package substrate, at least one integrated circuit comprising a topside connector or an edge connector to be coupled to a cable that is to couple to a cable receptacle.

Abstract: An on-package interface. A first set of single-ended transmitter circuits on a first die. The transmitter circuits are impedance matched and have no equalization. A first set of single-ended receiver circuits on a second die. The receiver circuits have no termination and no equalization. A plurality of conductive lines couple the first set of transmitter circuits and the first set of receiver circuits. The lengths of the plurality of conductive lines are matched.

Abstract: Apparatuses for interconnecting integrated circuit dies. A first set of single-ended transmitter circuits are included on a first die. The transmitter circuits are impedance matched and have no equalization. A first set of single-ended receiver circuits are included on a second die. The receiver circuits have no termination and no equalization. Conductive lines are coupled between the first set of transmitter circuits and the first set of receiver circuits. The lengths of the conductive lines are matched. The first die, the first set of single-ended transmitter circuits, the second die, the first set of single ended receiver circuits and the conductive lines are disposed within a first package. A second set of single-ended transmitter circuits are included on the first die. The transmitter circuits are impedance matched and have no equalization. Data transmitted from the second set of transmitter circuits is transmitted according to a data bus inversion (DBI) scheme.

Abstract: In one embodiment, the present invention includes a system having an electromagnetic coupler probe to electromagnetically sample signals from a device under test or a link under test and a receiver, e.g., configured as an integrated circuit that is to receive the sampled electromagnetic signals from the probe and output digital signals corresponding thereto. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a system having an electromagnetic coupler probe to electromagnetically sample signals from a device under test or a link under test and a receiver, e.g., configured as an integrated circuit that is to receive the sampled electromagnetic signals from the probe and output digital signals corresponding thereto. Other embodiments are described and claimed.

Abstract: In at least one embodiment an apparatus is provided that includes an electromagnetic coupler to provide sampled electromagnetic signals and an electronics component to receive the sampled electromagnetic signals from the electromagnetic coupler, to amplify and recover a derivative-like output signal, and to provide recovered sampled electromagnetic signals to an oscilloscope with a unity transfer function. Other embodiments may be described and claimed.

Abstract: In at least one embodiment an apparatus is provided that includes an electromagnetic coupler probe to provide sampled electromagnetic signals and an electronics component to receive the sampled electromagnetic signals from the electromagnetic coupler probe and to provide recovered sampled electromagnetic signals. Other embodiments may be described and claimed.

Abstract: In at least one embodiment an apparatus is provided that includes an electromagnetic coupler probe to provide sampled electromagnetic signals and an electronics component to receive the sampled electromagnetic signals from the electromagnetic coupler probe and to provide recovered sampled electromagnetic signals. Other embodiments may be described and claimed.