Abstract: Neutron detection cells and corresponding methods of detecting charged particles that make efficient use of silicon area are set forth. Three types of circuit cells/arrays are described: state latching circuits, glitch generating cells, and charge loss circuits. An array of these cells, used in conjunction with a neutron conversion film, increases the area that is sensitive to a strike by a charged particle over that of an array of SRAM cells. The result is a neutron detection cell that uses less power, costs less, and is more suitable for mass production.

Abstract: A receiver circuit is provided on an integrated circuit. The receiver circuit includes first and second power supply terminals, a ground supply terminal, a resistive element coupled between the first and second power supply terminals, and a receiver biased between the second power supply terminal and the ground supply terminal. The receiver draws a bias current through the resistive element, which varies as a positive function with a voltage on the second power supply terminal. The voltage on the second power supply terminal varies as an inverse function of the bias current.

Abstract: A method of manufacturing a neutron detector comprises forming a first wafer by at least forming an oxide layer on a substrate, forming an active semiconductor layer on the oxide layer, and forming an interconnect layer on the active semiconductor layer, forming at least one electrically conductive pathway extending from the interconnect layer through the active semiconductor layer and the oxide layer, forming a circuit transfer bond between the interconnect layer and a second wafer, removing the substrate of the first wafer after forming the circuit transfer bond, depositing a bond pad on the oxide layer after removing the substrate of the first wafer, wherein the bond pad is electrically connected to the electrically conductive pathway, depositing a barrier layer on the oxide layer after removing the substrate of the first wafer, and depositing a neutron conversion layer on the barrier layer after depositing the barrier layer.

Abstract: Neutron detection cells and corresponding methods of detecting charged particles that make efficient use of silicon area are set forth. Three types of circuit cells/arrays are described: state latching circuits, glitch generating cells, and charge loss circuits. An array of these cells, used in conjunction with a neutron conversion film, increases the area that is sensitive to a strike by a charged particle over that of an array of SRAM cells. The result is a neutron detection cell that uses less power, costs less, and is more suitable for mass production.

Abstract: A method of manufacturing a neutron detector comprises forming a first wafer by at least forming an oxide layer on a substrate, forming an active semiconductor layer on the oxide layer, and forming an interconnect layer on the active semiconductor layer, forming at least one electrically conductive pathway extending from the interconnect layer through the active semiconductor layer and the oxide layer, forming a circuit transfer bond between the interconnect layer and a second wafer, removing the substrate of the first wafer after forming the circuit transfer bond, depositing a bond pad on the oxide layer after removing the substrate of the first wafer, wherein the bond pad is electrically connected to the electrically conductive pathway, depositing a barrier layer on the oxide layer after removing the substrate of the first wafer, and depositing a neutron conversion layer on the barrier layer after depositing the barrier layer.

Abstract: A CMOS memory element comprising silicon-on-insulator MOSFET transistors is disclosed wherein at least one of the MOSFET transistors is configured such that the body of the transistor is not connected to a voltage source and is instead permitted to electrically float. Implementations of the disclosed memory element with increased immunity to errors caused by heavy ion radiation are also disclosed.

Abstract: A complementary metal-oxide-semiconductor (CMOS) static random-access-memory (SRAM) element comprising a planar metal-insulator-metal (MIM) capacitor is disclosed, and the planar MIM capacitor is electrically connected to the transistors in the CMOS memory element to reduce the effects of charged particle radiation on the CMOS memory element. Methods for immunizing a CMOS SRAM element to the effects of charged particle radiation are also disclosed, along with methods for manufacturing CMOS SRAM including planar MIM capacitors as integrated circuits.

Abstract: A method and apparatus are provided for protecting elements of a receiver from overvoltages in a pseudo-differential signal having a true signal and a reference voltage. The method and apparatus limit the true signal to a protection voltage, which is correlated to the reference voltage, to produce a protected true signal. The protected true signal and the reference voltage are applied to inputs of the receiver.

Abstract: A method and apparatus are provided for summing DC voltages, which employ at least one native transistor device to add a first DC input voltage to a second DC input voltage to produce a sum output.

Abstract: A process for forming a capacitive structure that includes an upper layer having a first capacitor electrode section therein. A capacitor dielectric layer is formed adjacent the upper layer. The capacitor dielectric layer covers the first capacitor electrode section. A second capacitor electrode layer is formed adjacent the capacitor dielectric layer. The second capacitor electrode layer includes a second capacitor electrode section that at least partially covers the first capacitor electrode section, and which has an edge portion that extends beyond the underlying first capacitor electrode section. The capacitor dielectric layer being disposed between the first capacitor electrode section and the second capacitor electrode section. An upper dielectric layer is formed adjacent the second capacitor electrode section.

Abstract: An apparatus comprising a first plurality of parallel switches and a second plurality of parallel switches. The first plurality of parallel switches may be configured to control a voltage on a first output pin. The second plurality of parallel switches may be configured to control a voltage on a second output pin. The first and second pluralities of parallel switches may be configured to provide rise time control of a differential waveform and be driven by a phased data signal.

Abstract: A core voltage to input output voltage level shifter of the type that uses a reference voltage source to generate a reference voltage to limit a drain voltage on at least one voltage sensitive node connected to a voltage sensitive switching device, that resides on a high voltage domain. A feed back line runs from the voltage sensitive node to the reference voltage source. A feed back structure varies the reference voltage in response to the drain voltage on the at least one voltage sensitive node, and thereby maintains the drain voltage at a substantially constant desired value.

Abstract: As technology in the semiconductor industry advances, semiconductor devices decrease in size to become faster and less expensive per function. Smaller semiconductor devices, particularly MOSFETs, are increasingly sensitive to Electrostatic Discharge (ESD). ESD can either destroy or permanently damage a semiconductor device. Embodiments of the present invention assist in preventing ESD damage to semiconductor devices. An embodiment of the present invention utilizes a diode connected to the substrate terminal of a MOSFET. Under normal operation up to the maximum operating voltage, the diode and MOS devices are open and do not conduct. The diode triggers when an ESD pulse causes the reverse breakdown voltage of the diode to be exceeded. The resultant current switches a connected MOS device, operating in bipolar mode, to dissipate the damaging ESD pulse. The ESD pulse is shunted to ground, thereby avoiding damage to the rest of the device.

Abstract: A varactor is formed with a semiconductor junction having a retrograde dopant concentration profile in a depletion region. The retrograde dopant concentration profile results in an approximately linear capacitance/voltage characteristic response of the varactor. The retrograde dopant concentration profile also enables a peak of the dopant concentration to function as a low resistance conductive path connecting to the varactor.

Abstract: A process for forming a capacitive structure that includes an upper layer having a first capacitor electrode section therein. A capacitor dielectric layer is formed adjacent the upper layer. The capacitor dielectric layer covers the first capacitor electrode section. A second capacitor electrode layer is formed adjacent the capacitor dielectric layer. The second capacitor electrode layer includes a second capacitor electrode section that at least partially covers the first capacitor electrode section, and which has an edge portion that extends beyond the underlying first capacitor electrode section. The capacitor dielectric layer being disposed between the first capacitor electrode section and the second capacitor electrode section. An upper dielectric layer is formed adjacent the second capacitor electrode section.

Abstract: A method of determining temperature of a semiconductor wafer during wafer fabrication includes the step of providing a response circuit on the semiconductor wafer. The method also includes the step of transmitting an interrogation signal with a signal transceiver so as to excite the response circuit. The method further includes the step of receiving a response signal which was generated by the response circuit as a result of excitation thereof. In addition, the method includes the step of determining temperature of the semiconductor wafer based on the response signal. Moreover, the method includes the step of fabricating a circuit layer on the semiconductor wafer. Both the transmitting step tri and the receiving step are performed contemporaneously with the fabricating step. An apparatus for determining temperature of a semiconductor wafer during wafer fabrication is also disclosed.

Abstract: As technology in the semiconductor industry advances, semiconductor devices decrease in size to become faster and less expensive per function. Smaller semiconductor devices, particularly MOSFETs, are increasingly sensitive to Electrostatic Discharge (ESD). ESD can either destroy or permanently damage a semiconductor device. Embodiments of the present invention assist in preventing ESD damage to semiconductor devices. An embodiment of the present invention utilizes a diode connected to the substrate terminal of a MOSFET. Under normal operation up to the maximum operating voltage, the diode and MOS devices are open and do not conduct. The diode triggers when an ESD pulse causes the reverse breakdown voltage of the diode to be exceeded. The resultant current switches a connected MOS device, operating in bipolar mode, to dissipate the damaging ESD pulse. The ESD pulse is shunted to ground, thereby avoiding damage to the rest of the device.

Abstract: As technology in the semiconductor industry advances, semiconductor devices decrease in size to become faster and less expensive per function. Smaller semiconductor devices, particularly MOSFETs, are increasingly sensitive to Electrostatic Discharge (ESD). ESD can either destroy or permanently damage a semiconductor device. Embodiments of the present invention assist in preventing ESD damage to semiconductor devices. An embodiment of the present invention utilizes a diode connected to the substrate terminal of a MOSFET. Under normal operation up to the maximum operating voltage, the diode and MOS devices are open and do not conduct. The diode triggers when an ESD pulse causes the reverse breakdown voltage of the diode to be exceeded. The resultant current switches a connected MOS device, operating in bipolar mode, to dissipate the damaging ESD pulse. The ESD pulse is shunted to ground, thereby avoiding damage to the rest of the device.

Abstract: A core voltage to input output voltage level shifter of the type that uses a reference voltage source to generate a reference voltage to limit a drain voltage on at least one voltage sensitive node connected to a voltage sensitive switching device, that resides on a high voltage domain. A feed back line runs from the voltage sensitive node to the reference voltage source. A feed back structure varies the reference voltage in response to the drain voltage on the at least one voltage sensitive node, and thereby maintains the drain voltage at a substantially constant desired value.

Abstract: A process for forming a capacitive structure that includes an upper layer having a first capacitor electrode section therein. A capacitor dielectric layer is formed adjacent the upper layer. The capacitor dielectric layer covers the first capacitor electrode section. A second capacitor electrode layer is formed adjacent the capacitor dielectric layer. The second capacitor electrode layer includes a second capacitor electrode section that at least partially covers the first capacitor electrode section, and which has an edge portion that extends beyond the underlying first capacitor electrode section. The capacitor dielectric layer being disposed between the first capacitor electrode section and the second capacitor electrode section. An upper dielectric layer is formed adjacent the second capacitor electrode section.