Abstract: A processor programmed to write to a memory location a first weighted value corresponding to the processor to overwrite a second weighted value stored in the memory location and associated with another processor. The processor is also programmed to compare the first weighted value of the processor with the second weighted value associated with the other processor and to select the processor if the first weighted value of the processor is better than the second weighted value.

Abstract: A system and method to determine a healthy group of processors and associated firmware for booting a system after a resetting event is disclosed. Redundant copies of processor specific firmware are examined for validity. Processors determine their own health status, and one processor determines a group of processors with the best available health status. Inter-processor interrupt messages provide the communication mechanism to allow an algorithm to determine a group of processors to continue booting the system.

Abstract: A processor programmed to write to a memory location a first weighted value corresponding to the processor to overwrite a second weighted value stored in the memory location and associated with another processor. The processor is also programmed to compare the first weighted value of the processor with the second weighted value associated with the other processor and to select the processor if the first weighted value of the processor is better than the second weighted value.

Abstract: A multiprocessor system includes an interconnection network, a shared resource coupled to the interconnection network and a plurality of processors coupled to each other and the shared resource via the interconnection network. The processors are programmed to associate a weighted value with each of the plurality of processors, compare the weighted values and select at least one of the processors from the plurality of processors based on the comparison of the weighted values.

Abstract: One embodiment of the invention provides a firmware architecture which splits firmware modules to support safe updates of specific modules as well as supporting multiple different processors. A firmware image is partitioned into several different binaries based on their update requirements and processor/platform dependence. A firmware interface table enables safe updates by enabling the option of redundant copies of specific modules as well as supporting systems with different and/or multiple processor types, mixed processors from the same family, and/or fault resilient firmware updates.

Abstract: A method and apparatus for asserting a signal that does one or more of (a) causing the computing device to enter a low power state, (b) turning the computing device off completely, or (c) resetting the computing device, in response to a received request from a remote device.

Abstract: The BIOS of a multiple processor system passes partial control to the operating system following an abbreviated power-on initialization. The BIOS program retains control of one or more processors and any memory that was untested during power-on. While the operating system is loaded and the system is operational, the BIOS program tests the retained memory. The BIOS program then relinquishes control of the retained memory and processor(s) during runtime to the operating system.

Abstract: The BIOS of a multiple processor system passes partial control to the operating system following an abbreviated power-on initialization. The BIOS program retains control of one or more processors and any memory that was untested during power-on. While the operating system is loaded and the system is operational, the BIOS program tests the retained memory. The BIOS program then relinquishes control of the retained memory and processor(s) during runtime to the operating system.

Abstract: One embodiment of the invention provides a firmware architecture which splits firmware modules to support safe updates of specific modules as well as supporting multiple different processors. A firmware image is partitioned into several different binaries based on their update requirements and processor/platform dependence. A firmware interface table enables safe updates by enabling the option of redundant copies of specific modules as well as supporting systems with different and/or multiple processor types, mixed processors from the same family, and/or fault resilient firmware updates.

Abstract: Cache defining arrangements for maximizing cacheable memory space, including a mixed technique scheme using a bottom-up scheme defining a first non-memory-hole portion using mainly substantially additive blocks of cacheable space, and a top-down scheme defining a second non-memory-hole portion by defining an oversized block of cacheable space and using mainly substantially subtractive blocks of cacheable space.

Abstract: A multiprocessor system includes an interconnection network, a shared resource coupled to the interconnection network and a plurality of processors coupled to each other and the shared resource via the interconnection network. The processors are programmed to associate a weighted value with each of the plurality of processors, compare the weighted values and select at least one of the processors from the plurality of processors based on the comparison of the weighted values.

Abstract: A system and method to determine a healthy group of processors and associated firmware for booting a system after a resetting event is disclosed. Redundant copies of processor specific firmware are examined for validity. Processors determine their own health status, and one processor determines a group of processors with the best available health status. Inter-processor interrupt messages provide the communication mechanism to allow an algorithm to determine a group of processors to continue booting the system.

Abstract: A method and apparatus for asserting a signal that does one or more of (a) causing the computing device to enter a low power state, (b) turning the computing device off completely, or (c) resetting the computing device, in response to a received request from a remote device.

Abstract: Cache defining arrangements for maximizing cacheable memory space.

Abstract: Optional features of a computer system are enabled securely. Examples of the system features generally include number of processors, processor speed, memory size, and bus speed. A BIOS (Basic Input/Output System) of the system receives encrypted feature packets from a manufacturer of the system, decrypts, authenticates, and verifies the packets, and stores the decrypted packets in a secure, non-volatile storage. When the system is rebooted, the BIOS enables the optional system features as specified in the feature packets. Accordingly, the optional system features are enabled in a secure manner.

Abstract: A method for tracking agents across loss of state events is described. After determining the number of terminal agents within a hierarchical agent system, an algorithm forms a first matrix containing data identifying agents within the hierarchical agent system. After a potential loss of state event has occurred, the algorithm forms a second matrix containing data identifying agents within the hierarchical agent system and compares the first matrix to the second matrix. If the matrices are identical, no agent switch occurred during the potential loss of state event. If the matrices are not identical, at least one agent switch occurred during the potential loss of state event.

Abstract: The BIOS of a multiple processor system passes partial control to the operating system following an abbreviated power-on initialization. The BIOS program retains control of one or more processors and any memory that was untested during power-on. While the operating system is loaded and the system is operational, the BIOS program tests the retained memory. The BIOS program then relinquishes control of the retained memory and processor(s) during runtime to the operating system.