Abstract: Various embodiments of a method and apparatus for flushing a cache are disclosed. In a system, a cache memory is accessible by an execution circuit. The execution circuit executes instructions and may utilize data and/or instructions stored in the cache. A flush circuit is also coupled to the cache. Responsive to execution of a power down instruction by the execution circuit, the flush circuit performs a cache flush. If a control state is asserted in a control register, the flush circuit generates a dummy event upon completing the cache flush. Responsive to generating the dummy event, a processor core that includes the execution circuit is inhibited from being powered down.

Abstract: A system provides complex branch execution hardware and a hardware-based Multiplexer (MUX) to multiplex a fetch address of a future branch and a preloaded branch fetch address to create an index hash value that is used to index a branch target prediction table for execution by a processor core, in order to reduce branch mis-prediction by preloading.

Abstract: There is provided a method and system for replacing an instruction with another instruction. A match register stores an opcode that identifies an instruction to be replaced. A swap register stores an instruction that replaces the identified instruction. A multiplexer chooses the instruction stored in the swap register over the identified instruction if predecode bits of the identified instruction are set.

Abstract: A system and a method for simulation using multiple programming languages is provided. The method can include receiving an annotated source having a first plurality of instructions written in a first programming language and receiving an annotation having a second plurality of instructions written in a second programming language and associated with an annotated instruction from the first plurality of instructions. The method can include extracting the second plurality of instructions to create a routine from the annotation. The method can include building a shared library that contains the routine. The method can include building an application object file by assigning an address to each instruction of the first plurality instructions. The method can include creating an annotation table that contains an address for the annotated instruction and an associated symbol.

Abstract: A system and a method for simulation using multiple programming languages is provided. The method can include receiving an annotated source having a first plurality of instructions written in a first programming language and receiving an annotation having a second plurality of instructions written in a second programming language and associated with an annotated instruction from the first plurality of instructions. The method can include extracting the second plurality of instructions to create a routine from the annotation. The method can include building a shared library that contains the routine. The method can include building an application object file by assigning an address to each instruction of the first plurality instructions. The method can include creating an annotation table that contains an address for the annotated instruction and an associated symbol.

Abstract: There is provided a method and system for replacing an instruction with another instruction. A match register stores an opcode that identifies an instruction to be replaced. A swap register stores an instruction that replaces the identified instruction. A multiplexer chooses the instruction stored in the swap register over the identified instruction if predecode bits of the identified instruction are set.

Abstract: A method for double-issue complex instructions receives a complex instruction comprising a first portion and a second portion. The method sets a single issue queue slot and allocates an execution unit for the complex instruction, and identifies dependencies in the first and second portions. The method sets a dependency matrix slot and a consumers table slot for the first and section portion. In the event the first portion dependencies have been satisfied, the method issues the first portion and then issues the second portion from the single issue queue slot. In the event the second portion dependencies have not been satisfied, the method cancels the second portion issue.

Abstract: A method receives a complex instruction comprising a first portion and a second portion. The method sets a single issue queue slot and allocates an execution unit for the complex instruction, and identifies dependencies in the first and second portions. The method sets a dependency matrix slot and a consumers table slot for the first and section portion. In the event the first portion dependencies have been satisfied, the method issues the first portion and then issues the second portion from the single issue queue slot. In the event the second portion dependencies have not been satisfied, the method places the second portion into a side issue queue. The method issues the second portion when the side issue queue indicates that the second portion is eligible for issue.

Abstract: A design structure for resolving the occurrence of livelock at the interface between the processor core and memory subsystem controller. Livelock is resolved by introducing a livelock detection mechanism (which includes livelock detection utility or logic) within the processor to detect a livelock condition and dynamically change the duration of the delay stage(s) in order to alter the “harmonic” fixed-cycle loop behavior. The livelock detection logic (LDL) counts the number of flushes a particular instruction takes or the number of times an instruction re-issues without completing. The LDL then compares that number to a preset threshold number. Based on the result of the comparison, the LDL triggers the implementation of one of two different livelock resolution processes.

Abstract: A mechanism is provided for tracking deallocated load instructions. A processor detects whether a load instruction in a set of instructions in an issue queue has missed. Responsive to a miss of the load instruction, an instruction scheduler allocates the load instruction to a load miss queue and deallocates the load instruction from the issue queue. The instruction scheduler determines whether there is a dependence entry for the load instruction in an issue queue portion of a dependence matrix. Responsive to the existence of the dependence entry for the load instruction in the issue queue portion of the dependence matrix, the instruction scheduler reads data from the dependence entry of the issue queue portion of the dependence matrix that specifies a set of dependent instructions that are dependent on the load instruction and writes the data into a new entry in a load miss queue portion of the dependence matrix.

Abstract: A design structure embodied in a non-transitory machine readable medium used in a design process includes an apparatus for implementing speculative clock gating of digital logic circuits, including operation valid logic configured to generate, in a first pipeline stage n, a valid control signal input to a first register in a second pipeline stage n+1, the valid control signal indicative of when an operation is qualified to be performed by the second pipeline stage n+1; and speculative valid logic configured to generate, in the first pipeline stage, a speculative valid control signal used to gate a clock signal to a plurality of additional registers in the second pipeline stage, wherein the speculative valid control signal is generated using only a subset of a total number of control inputs used in generating the valid control signal, and wherein the clock signal is sent directly to the first register.

Abstract: A mechanism is provided for issuing instructions. An instruction dispatch unit receives an instruction for dispatch to one of a plurality of execution units. The instruction dispatch unit analyzes a tag register to determine whether a previous tag associated with a previous instruction has been stored in the tag register. Responsive to the previous tag associated with the previous instruction failing to be stored in the tag register, the instruction dispatch unit storing a tag corresponding to the instruction in the tag register. The instruction dispatch unit dispatches the instruction to an issue queue for issue to the one of the plurality of execution units.

Abstract: A system and method for issuing load-dependent instructions in an issue queue in a processing unit. A load miss queue is provided. The load miss queue comprises a physical address field, an issue queue position field, a valid identifier field, a source identifier field, and a data type field. A load instruction that misses a first level cache is dispatched, and both the physical address field and the data type field are set. A load-dependent instruction is identified. In response to identifying the load-dependent instruction, each of the issue queue position field, valid identifier field, and source identifier field are set. If the issue queue position field refers to a flushed instruction, the valid identifier field is cleared. The load instruction is recycled, and a value of the valid identifier field is determined. The load-dependent instruction is then selected for issue on a next processing cycle independent of an age of the load-dependent instruction.

Abstract: A method for implementing speculative clock gating of digital logic circuits in a multiple stage pipeline design includes generating, in a first pipeline stage n, a valid control signal that is input to a first register in a second pipeline stage n+1, the valid control signal indicative of when an operation is qualified to be performed by the second pipeline stage n+1; and generating, in the first pipeline stage, a speculative valid control signal that is used to gate a clock signal to a plurality of additional registers in the second pipeline stage, wherein the speculative valid control signal is generated using only a subset of a total number of control inputs used in generating the valid control signal, and wherein the clock signal is sent directly, without gating, to the first register in the second pipeline stage.

Abstract: A processor having a dependency matrix comprises a first array comprising a plurality of cells arranged in a plurality of columns and a plurality of rows. Each row represents an instruction in a processor execution queue and each cell represents a dependency relationship between two instructions in the processor execution queue. A first latch couples to the first array and comprises a first bit, the first bit indicating a first status. A second latch couples to the first array and comprises a second bit, the second bit indicating a second status. A first read port couples to the first array, comprising a first read wordline and a first read bitline. The first read wordline couples to the first latch and a first column and asserts a first available signal based on the first bit. The first read bitline couples to a first row and generates a first ready signal based on the first available signal and a first cell.

Abstract: A processor having a dependency matrix comprises a first array comprising a plurality of cells arranged in a plurality of columns and a plurality of rows. Each row represents an instruction in a processor execution queue and each cell in the first array represents a dependency relationship between two instructions in the processor execution queue. A clear port couples to the first array and clears a column of the first array. A producer status module couples to the clear port and the first array and determines an execution status of a producer instruction, wherein the producer instruction is an instruction in the processor execution queue. An available-status port couples to the first array and the producer status module and sets a read wordline column corresponding to the producer instruction based on the execution status of the producer instruction. The available-status port deasserts the read wordline column in response to a selection of the producer for execution.

Abstract: A mechanism is provided for tracking deallocated load instructions. A processor detects whether a load instruction in a set of instructions in an issue queue has missed. Responsive to a miss of the load instruction, an instruction scheduler allocates the load instruction to a load miss queue and deallocates the load instruction from the issue queue. The instruction scheduler determines whether there is a dependence entry for the load instruction in an issue queue portion of a dependence matrix. Responsive to the existence of the dependence entry for the load instruction in the issue queue portion of the dependence matrix, the instruction scheduler reads data from the dependence entry of the issue queue portion of the dependence matrix that specifies a set of dependent instructions that are dependent on the load instruction and writes the data into a new entry in a load miss queue portion of the dependence matrix.

Abstract: A mechanism is provided for issuing instructions. An instruction dispatch unit receives an instruction for dispatch to one of a plurality of execution units. The instruction dispatch unit analyzes a tag register to determine whether a previous tag associated with a previous instruction has been stored in the tag register. Responsive to the previous tag associated with the previous instruction failing to be stored in the tag register, the instruction dispatch unit storing a tag corresponding to the instruction in the tag register. The instruction dispatch unit dispatches the instruction to an issue queue for issue to the one of the plurality of execution units.

Abstract: A system and method for issuing load-dependent instructions in an issue queue in a processing unit. A load miss queue is provided. The load miss queue comprises a physical address field, an issue queue position field, a valid identifier field, a source identifier field, and a data type field. A load instruction that misses a first level cache is dispatched, and both the physical address field and the data type field are set. A load-dependent instruction is identified. In response to indentifying the load-dependent instruction, each of the issue queue position field, valid identifier field, and source identifier field are set. If the issue queue position field refers to a flushed instruction, the valid identifier field is cleared. The load instruction is recycled, and a value of the valid identifier field is determined. The load-dependent instruction is then selected for issue on a next processing cycle independent of an age of the load-dependent instruction.

Abstract: A method for double-issue complex instructions receives a complex instruction comprising a first portion and a second portion. The method sets a single issue queue slot and allocates an execution unit for the complex instruction, and identifies dependencies in the first and second portions. The method sets a dependency matrix slot and a consumers table slot for the first and section portion. In the event the first portion dependencies have been satisfied, the method issues the first portion and then issues the second portion from the single issue queue slot. In the event the second portion dependencies have not been satisfied, the method cancels the second portion issue.