Abstract: A video port aggregator receives plural asynchronous video data streams. Corresponding input buffers generate video data and a status signal. A memory controller writes the video data in corresponding locations within an external memory. A channel triggers the memory controller to read data out of the external memory for transmission to a single video output port when said corresponding status signal indicates receipt of a predetermined portion of data. This read out of the external memory being faster than the writing. The channel sequencer triggers the memory controller to read data out of the external memory video data of a highest priority asynchronous video data stream having a received next portion of data.

Abstract: A system and method for allocating video processing tasks over multiple video processors include an apparatus. The apparatus includes a plurality of video processors. Each video processor includes a first processor that processes video data and manages buffers used in conversion and displaying video data. The video processor includes a second processor that performs video data signal processing and manages buffers used in processing video data. The apparatus also includes a switch coupled to each video processor, as well as video inputs and video outputs. A third processor coupled to the switch, and a memory coupled to each video processor and to the third processor, are also part of the apparatus. The switch selectively couples a video processor to a video input or a video output, the third processor configures the switch based on processing requirements of each video stream, and the memory buffers and stores video data.

Abstract: A system and method for allocating video processing tasks over multiple video processors include an apparatus. The apparatus includes a plurality of video processors. Each video processor includes a first processor that processes video data and manages buffers used in conversion and displaying video data. The video processor includes a second processor that performs video data signal processing and manages buffers used in processing video data. The apparatus also includes a switch coupled to each video processor, as well as video inputs and video outputs. A third processor coupled to the switch, and a memory coupled to each video processor and to the third processor, are also part of the apparatus. The switch selectively couples a video processor to a video input or a video output, the third processor configures the switch based on processing requirements of each video stream, and the memory buffers and stores video data.

Abstract: A video port aggregator receives plural asynchronous video data streams. Corresponding input buffers generate video data and a status signal. A memory controller writes the video data in corresponding locations within an external memory. A channel triggers the memory controller to read data out of the external memory for transmission to a single video output port when said corresponding status signal indicates receipt of a predetermined portion of data. This read out of the external memory being faster than the writing. The channel sequencer triggers the memory controller to read data out of the external memory video data of a highest priority asynchronous video data stream having a received next portion of data.