Abstract: A range finding audio system automatically modifies the audio output of an audio source based on the distance of a listener from the speakers. A speaker in an audio system may include a range device coupled with a controller. The range device may utilize infrared, laser, or acoustic technology to determine the distance between the speaker and the listener. The controller may transfer distance information to an audio interface of a processor unit. The audio lo interface may include a positioning routine to modify the audio output according to the distance from the speaker to the listener. Alternatively, the controller may perform the functions ascribed to the positioning routine making the necessary modifications to the audio output based on the distance information.

Abstract: A range finding audio system automatically modifies the audio output of an audio source based on the distance of a listener from the speakers. A speaker in an audio system may include a range device coupled with a controller. The range device may utilize infrared, laser, or acoustic technology to determine the distance between the speaker and the listener. The controller may transfer distance information to an audio interface of a processor unit. The audio lo interface may include a positioning routine to modify the audio output according to the distance from the speaker to the listener. Alternatively, the controller may perform the functions ascribed to the positioning routine making the necessary modifications to the audio output based on the distance information.

Abstract: One embodiment of the present invention relates to a method for using at least two first-in, first-out (“FIFO”) buffers in a pipelined bus, comprising, interlocking the at least two FIFO buffers, wherein the act of interlocking comprises defining a transaction correspondence between the phases tracked by each of the buffers.

Abstract: A range finding audio system automatically modifies the audio output of an audio source based on the distance of a listener from the speakers. A speaker in an audio system may include a range device coupled with a controller. The range device may utilize infrared, laser, or acoustic technology to determine the distance between the speaker and the listener. The controller may transfer distance information to an audio interface of a processor unit. The audio interface may include a positioning routine to modify the audio output according to the distance from the speaker to the listener. Alternatively, the controller may perform the functions ascribed to the positioning routine making the necessary modifications to the audio output based on the distance information.

Abstract: One embodiment of the present invention relates to a method for using at least two first-in, first-out (“FIFO”) buffers in a pipelined bus, comprising, interlocking the at least two FIFO buffers, wherein the act of interlocking comprises defining a transaction correspondence between the phases tracked by each of the buffers.

Abstract: One embodiment of the present invention relates to a method for using at least two first-in, first-out (“FIFO”) buffers in a pipelined bus, comprising, interlocking the at least two FIFO buffers, wherein the act of interlocking comprises defining a transaction correspondence between the phases tracked by each of the buffers.

Abstract: One embodiment of the present invention relates to a method for using at least two first-in, first-out (“FIFO”) buffers in a pipelined bus, comprising, interlocking the at least two FIFO buffers, wherein the act of interlocking comprises defining a transaction correspondence between the phases tracked by each of the buffers.

Abstract: One embodiment of the present invention relates to a method for using at least two first-in, first-out (“FIFO”) buffers in a pipelined bus, comprising, interlocking the at least two FIFO buffers, wherein the act of interlocking comprises defining a transaction correspondence between the phases tracked by each of the buffers.

Abstract: The present invention provides a circuit for saving overflow data within a sequence of data that are to be clocked out of a sequential storage device. The sequential storage device has a data output to clock out data in response to a flow control signal being asserted. The sequential storage device terminates this clocking out of the data in response to the flow control signal being deasserted. However, overflow data may be relinquished by the sequential storage device and clocked out of the data output even after the flow control signal has been deasserted. The circuit includes a slack register that is connected to the data output of the sequential storage device. The slack register stores the overflow data for when the flow control signal is again asserted.

Abstract: A technique to provide device status information includes obtaining device status information, determining when a bus retry operation is being executed, and routing the device status information to a bus if a bus retry operation is being executed.

Abstract: A buffer pool is described for buffering data transfers between components within a computer system. The buffer pool uses a translation table to translate virtual address pointers from calling computer components into physical address pointers within a line buffer array. The virtual address pointers are held in a translation entry table that correlates virtual and physical pointers.

Abstract: One embodiment of the present invention relates to a method for using at least two first-in, first-out (“FIFO”) buffers in a pipelined bus, comprising, interlocking the at least two FIFO buffers, wherein the act of interlocking comprises defining a transaction correspondence between the phases tracked by each of the buffers.

Abstract: A technique to provide device status information includes obtaining device status information, determining when a bus retry operation is being executed, and routing the device status information to a bus if a bus retry operation is being executed.

Abstract: The present invention provides a circuit for saving overflow data within a sequence of data that are to be clocked out of a sequential storage device. The sequential storage device has a data output to clock out data in response to a flow control signal being asserted. The sequential storage device terminates this clocking out of the data in response to the flow control signal being deasserted. However, overflow data may be relinquished by the sequential storage device and clocked out of the data output even after the flow control signal has been deasserted. The circuit includes a slack register that is connected to the data output of the sequential storage device. The slack register stores the overflow data for when the flow control signal is again asserted.

Abstract: A method is described for buffering data transfers between components within a computer system. The method uses a buffer pool and translation table to translate virtual address pointers from calling computer components into physical address pointers within a line buffer array. The virtual address pointers are then held in a translation entry table that correlates the virtual and physical pointers.

Abstract: One embodiment of the present invention provides a method for outputting a sequence of items from a sequential storage device having a data output. The data items are clocked onto the data output when a flow control signal is being asserted. A data item that is on the data output when the flow control signal is deasserted is saved in a slack register for later use to maintain the sequence of data.

Abstract: A bi-directional buffer circuit for transferring data between clock boundaries in a computer system is described. The circuit is divided into halves, with one half being controlled by a first clock and the second half being controlled by a second clock. The incoming data that is synchronized to the first clock is compiled into data blocks and stored into registers before being synchronized and transferred to the other half of the circuit. The data blocks that are stored in the register sent across a the clock boundary the then synchronized into matched registers within the second half of the circuit. In addition, the signals that control the synchronization of data blocks between the halves of the circuit are synchronized by two stages of registers to avoid the problem the metastability.

Abstract: A bi-directional buffer circuit for transferring data between clock boundaries in a computer system is described. The circuit is divided into halves, with one half being controlled by a first clock and the second half being controlled by a second clock. The incoming data that is synchronized to the first clock is compiled into data blocks and stored into registers before being synchronized and transferred to the other half of the circuit. The data blocks that are stored in the register sent across a the clock boundary the then synchronized into matched registers within the second half of the circuit. In addition, the signals that control the synchronization of data blocks between the halves of the circuit are synchronized by two stages of registers to avoid the problem of metastability.

Abstract: A graphics accelerator chip which interprets instructions and data transferred from a microprocessor via an external data bus logically coupled to the microprocessor. A host logic interface buffers the information received from the microprocessor with an on-chip first-in first-out (FIFO) memory which has an address space mapped onto a contiguous sequential address space of the microprocessor. A state machine having a temporary memory receives and interprets instructions and data from the FIFO memory, and routes them to a graphics register set which performs logical graphics operations based upon the graphics instructions and data. The temporary memory stores the last primitive command received, allowing the chip to perform multiple graphics operations where a primitive command is received from the microprocessor only once. A separate data bus from the host logic interface to the graphics register set enables direct access to the graphics registers from the microprocessor.