Abstract: An amplifier includes an amplifier section having selectable signal paths to provide discrete gain settings, and logic to incrementally select the signal paths. The logic may be configured to increment the gain in response to digital gain control signals or an analog gain control signal. Another amplifier has an input section with one or more input cells and an output section with one or more output cells. Either the input section or the output section includes at least two cells that may be selected to provide discrete gain settings. A loop amplifier is configured in a feedback arrangement with the input section. The input and output sections may have multiple selectable cells to provide coarse and fine gain steps. The gain of the loop amplifier may be coordinated with the gain of the input section to provide constant bandwidth operation.

Abstract: An amplifier includes an amplifier section having selectable signal paths to provide discrete gain settings, and logic to incrementally select the signal paths. The logic may be configured to increment the gain in response to digital gain control signals or an analog gain control signal. Another amplifier has an input section with one or more input cells and an output section with one or more output cells. Either the input section or the output section includes at least two cells that may be selected to provide discrete gain settings. A loop amplifier is configured in a feedback arrangement with the input section. The input and output sections may have multiple selectable cells to provide coarse and fine gain steps. The gain of the loop amplifier may be coordinated with the gain of the input section to provide constant bandwidth operation.

Abstract: A selectable gain amplifier includes two or more selectable gain stages, each gain stage having a first input coupled to receive an input signal, a second input, and an output. The amplifier further includes and two or more feedback paths coupled between the outputs and the second inputs of the selectable gain stages.

Abstract: A variable gain amplifier includes an attenuator having a plurality of pairs of tap points, and a plurality of pairs of gm cells, wherein each pair of gm cells is coupled to a corresponding pair of the tap points, and each pair of gm cells is constructed and arranged to operate as a multi-tanh cell.

Abstract: An amplifier includes an amplifier section having selectable signal paths to provide discrete gain settings, and logic to incrementally select the signal paths. The logic may be configured to increment the gain in response to digital gain control signals or an analog gain control signal. Another amplifier has an input section with one or more input cells and an output section with one or more output cells. Either the input section or the output section includes at least two cells that may be selected to provide discrete gain settings. A loop amplifier is configured in a feedback arrangement with the input section. The input and output sections may have multiple selectable cells to provide coarse and fine gain steps. The gain of the loop amplifier may be coordinated with the gain of the input section to provide constant bandwidth operation.

Abstract: An amplifier includes an amplifier section having selectable signal paths to provide discrete gain settings, and logic to incrementally select the signal paths. The logic may be configured to increment the gain in response to digital gain control signals or an analog gain control signal. Another amplifier has an input section with one or more input cells and an output section with one or more output cells. Either the input section or the output section includes at least two cells that may be selected to provide discrete gain settings. A loop amplifier is configured in a feedback arrangement with the input section. The input and output sections may have multiple selectable cells to provide coarse and fine gain steps. The gain of the loop amplifier may be coordinated with the gain of the input section to provide constant bandwidth operation.

Abstract: A variable gain amplifier includes an attenuator having a plurality of pairs of tap points, and a plurality of pairs of gm cells, wherein each pair of gm cells is coupled to a corresponding pair of the tap points, and each pair of gm cells is constructed and arranged to operate as a multi-tanh cell.

Abstract: A selectable gain amplifier includes two or more selectable gain stages, each gain stage having a first input coupled to receive an input signal, a second input, and an output. The amplifier further includes and two or more feedback paths coupled between the outputs and the second inputs of the selectable gain stages.

Abstract: A variable gain amplifier includes an attenuator having a plurality of pairs of tap points, and a plurality of pairs of gm cells, wherein each pair of gm cells is coupled to a corresponding pair of the tap points, and each pair of gm cells is constructed and arranged to operate as a multi-tanh cell.

Abstract: An amplifier has an input terminal to receive an input signal. The amplifier includes a first gain stage comprising a pair of input transistors and a second gain stage to drive an output stage. The output stage provides inverting and non-inverting differential output signals on inverting and non-inverting output nodes. The amplifier may also include a feedback signal electrically connected between the inverting and non-inverting output nodes to emitters of the input transistors through a resistor network.

Abstract: A rate 2/5 (2,18,2) code especially suitable for use with a resonant coil overwrite technique for magneto-optical recording. Serial binary input data is converted to serial binary code data that satisfies a (2,18,2) constraint and is reconverted to the serial binary input data. An encoder receives two sequential input bits and a five-bit state vector derived from an immediately preceding encoding operation, and generates a five-bit codeword and a new five-bit state vector based on the two input bits and five-bit state vector. A decoder converts the binary code data into five-bit codewords, converts each five-bit codeword sequentially into a reassigned three-bit codeword representation, then collects sets of four adjacent three-bit codeword representations. Each reassigned codeword representation is converted to a two-bit output corresponding to a then current set of said four three-bit codeword representations, and successive two-bit outputs are reconverted into the serial binary data.