Abstract: Physical or off-chip interfaces may be selectively bypassed in a boundary scan chain. A bypass control signal may be produced that indicates whether to bypass a selected one of the interfaces. In response to a first state of a bypass control signal, a multiplexer may couple the scan chain output of an interface boundary scan cell to the scan chain input of a successor boundary scan cell of the interface boundary scan cell. In response to a second state of the bypass control signal, the multiplexer may couple the scan chain output of a predecessor boundary scan cell of the interface boundary scan cell to the scan chain input of the successor boundary scan cell, bypassing the interface boundary scan cell.

Abstract: Systems and method are directed to Universal Flash Storage (UFS) memory system configured to support deep power-down modes wherein the UFS memory system is not required to be responsive to commands received from a host device coupled to the UFS memory system. Correspondingly, in the deep power-down modes, a link or interface between the UFS memory system and the host device may also be powered down. The UFS memory system may enter the deep power-down modes based on a command received from the host device or a hardware reset assertion, and exit the deep power-down modes based on a hardware reset de-assertion or power cycling. While in deep power-down modes, the power consumption of the UFS memory device is substantially lower than the power consumption of the UFS memory device in conventional power modes.

Abstract: Various embodiments include a shared power rail monitoring circuit included in integrated circuits configured to manage worst case power on a shared power rail within the integrated circuit. Various embodiments include circuit components configured to determine allocated currents for each processing block or subsystem core on the shared power rail based on operating parameters of each processing block or subsystem core, and set a mitigation level for one or more processing blocks or subsystem cores on the shared power rail based at least in part on the determined allocated currents for each processing block or subsystem core on the shared power rail. The operating parameters may be voltage or voltage mode, temperature and operating frequency of each processing block or subsystem core.

Abstract: Systems and method are directed to Universal Flash Storage (UFS) memory system configured to support deep power-down modes wherein the UFS memory system is not required to be responsive to commands received from a host device coupled to the UFS memory system. Correspondingly, in the deep power-down modes, a link or interface between the UFS memory system and the host device may also be powered down. The UFS memory system may enter the deep power-down modes based on a command received from the host device or a hardware reset assertion, and exit the deep power-down modes based on a hardware reset de-assertion or power cycling. While in deep power-down modes, the power consumption of the UFS memory device is substantially lower than the power consumption of the UFS memory device in conventional power modes.

Abstract: Systems and method are directed to Universal Flash Storage (UFS) memory system configured to support deep power-down modes wherein the UFS memory system is not required to be responsive to commands received from a host device coupled to the UFS memory system. Correspondingly, in the deep power-down modes, a link or interface between the UFS memory system and the host device may also be powered down. The UFS memory system may enter the deep power-down modes based on a command received from the host device or a hardware reset assertion, and exit the deep power-down modes based on a hardware reset de-assertion or power cycling. While in deep power-down modes, the power consumption of the UFS memory device is substantially lower than the power consumption of the UFS memory device in conventional power modes.

Abstract: Systems, methods, and apparatus for communicating a control signal between device components are provided. Within an apparatus, an integrated circuit (IC) sends a control signal to a system on chip (SoC). The control signal requests enablement or disablement of one or more resources corresponding to the IC. Thereafter, a converting circuit within the SoC converts the control signal from the IC into a command to be transmitted to one or more devices. The converting circuit then transmits the command to the one or more devices via a bus coupling the SoC to the one or more devices. The one or more devices includes one or more power management integrated circuits (PMICs) configured to control the one or more resources.

Abstract: Systems and method are directed to Universal Flash Storage (UFS) memory system configured to support deep power-down modes wherein the UFS memory system is not required to be responsive to commands received from a host device coupled to the UFS memory system. Correspondingly, in the deep power-down modes, a link or interface between the UFS memory system and the host device may also be powered down. The UFS memory system may enter the deep power-down modes based on a command received from the host device or a hardware reset assertion, and exit the deep power-down modes based on a hardware reset de-assertion or power cycling. While in deep power-down modes, the power consumption of the UFS memory device is substantially lower than the power consumption of the UFS memory device in conventional power modes.

Abstract: A ten sided die within a translucent or transparent 6-sided die that is used for generation of numbers from zero through 59, primarily for the generation of lottery numbers.