Abstract: A substrate includes a location for coupling one or more chiplets to the substrate. The location has dimensions that bound dimensions of chiplets capable of being coupled to the substrate in the location. Additionally, the location includes an interface region having connections for one or more die-to-die interfaces of the one or more chiplets and a power region that includes a power interface having connections for the one or more chiplets.

Abstract: The disclosed device includes a communication link between chiplets and a control circuit near a physical layer of the link for one of the chiplets. When the link becomes inactive, the control circuit can mimic an active status of the link including intercepting packets and injecting mimicked responses, to allow graceful failover or other debugging. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A method for performing data communication over a data communications bus can include detecting, by at least one processor, a failure of at least one communications channel of two or more communications channels of a data communications bus based at least in part on a header verification code included in a header of a first packet that was communicated over the two or more communications channels. The method can also include performing, by the at least one processor, data communication of a second packet over a subset of the two or more communications channels that excludes the at least one communications channel based on the failure of the at least one communications channel. Various other methods and systems are also disclosed.

Abstract: The disclosed semiconductor package includes a first chiplet area for receiving a first chiplet, a second chiplet area for receiving a second chiplet, and a host die coupled to the first and second chiplet areas. The semiconductor package also includes an interconnect directly coupling the first chiplet area to the second chiplet area. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: Programmable I/O die devices and methods are described. An example system includes an input/output die (IOD) that couples a plurality of devices. The system also includes a programmable fabric included in the IOD. The programmable fabric implements interconnects for connecting the plurality of devices according to a reconfigurable topology defined by a configuration of the programmable fabric.

Abstract: The disclosed semiconductor package includes a first chiplet area for receiving a first chiplet, a second chiplet area for receiving a second chiplet, and a host die coupled to the first and second chiplet areas. The semiconductor package also includes an interconnect directly coupling the first chiplet area to the second chiplet area. Various other methods, systems, and computer-readable media are also disclosed.

Abstract: A substrate includes a location for coupling one or more chiplets to the substrate. The location has dimensions that bound dimensions of chiplets capable of being coupled to the substrate in the location. Additionally, the location includes an interface region having connections for one or more die-to-die interfaces of the one or more chiplets and a power region that includes a power interface having connections for the one or more chiplets.