Abstract: A computer system includes a CPU and a memory device coupled by a North bridge logic unit to an expansion bus, such as a PCI bus. A South bridge logic connects to the expansion bus and couples various secondary busses and peripheral devices to the expansion bus. The South bridge logic includes internal control devices or master devices that are designed to run master cycles on the expansion bus. The master devices couple to the expansion bus through a common expansion master interface, which executes master cycles on the expansion bus on behalf of the master devices. The South bridge also includes an internal modular master expansion bus coupling the internal master devices to the common master interface. The internal modular master expansion bus permits the master devices to run master cycles to any expansion bus by understanding a standardized group of signals represented by the internal modular master expansion (IMAX) bus.

Abstract: A computer system includes a secondary bus bridge device in a portable computer and a another secondary bus bridge device in an expansion base to which the portable computer connects (docks). A peripheral in the expansion base may initiate a delayed cycle to read or write data to memory through a primary bus bridge device that also couples to a CPU. Both secondary bus bridge devices include an arbiter for controlling arbitration of a peripheral bus that connects both secondary bridge devices. The arbiter in the secondary bridge of the portable computer determines which of the arbiters will have arbitration control of the expansion bus to run cycles. When read data is available, in the case of a delayed read cycle initiated by a peripheral device in the expansion base, the primary bridge strobes a delayed cycle control signal to the arbiter in the portable computer which then gives arbitration control to the arbiter in the expansion base.

Abstract: A computer system includes a South bridge logic that connects an expansion bus to one or more secondary expansion busses and peripheral devices. The South bridge logic includes internal control devices that are targets for masters on the expansion bus. The target devices couple to the expansion bus through a common expansion target interface, which monitors and translates master cycles on the expansion bus on behalf of the target devices. The South bridge includes an ACPI/power management logic capable of supporting a Device Idle mode in which selected I/O device may be placed in a low power state. To prevent cycles from being run to a device in a low power state, the ACPI/power management includes status registers that are used to determine when a device in low power mode is the target of an expansion bus cycle. If such a cycle occurs, the cycle is intercepted and an SMI signal is transmitted to the CPU. In addition, the target interface responds to the master by asserting a retry signal.

Abstract: A computer system including a programmable bridge logic device to disable various peripheral device functions is disclosed. The bridge logic device preferably includes an address decoder and one or more peripheral bus controllers. The address decoder preferably includes a configuration disable unit comprising one or more programmable status bits. Each status bit is associated with a particular peripheral device function, such as a IDE or USB functions. When a status bit is set, configuration cycles to the function corresponding to that bit are disabled. In one aspect of the invention, the computer system comprises a laptop computer that can be docked to an expansion base. The laptop and the expansion base may duplicate one or more functions. When docked, the status bit in the bridge device associated with a function also provided in the expansion base is set disabling the duplicate function in the laptop in favor of the function in the expansion base.

Abstract: A computer system includes a CPU and a memory device coupled by a North bridge logic unit to an expansion bus, such as a PCI bus. A South bridge logic connects to the expansion bus and couples various secondary busses and peripheral devices to the expansion bus. The South bridge logic includes internal control devices that are targets for masters on the expansion bus. The target devices couple to the expansion bus through a common expansion target interface, which monitors and translates master cycles on the expansion bus on behalf of the target devices. The South bridge also includes an internal modular target expansion bus coupling the internal target devices to the common target interface. The internal modular target expansion bus permits the target devices to receive master cycles from any expansion bus by understanding a standardized group of signals represented by the internal modular target expansion (IMAX) bus.

Abstract: A computer system includes an I/O controller and a bridge logic device which transmit status data via a serial bus. The I/O controller comprises an embedded controller, a memory device, and a serial bus interface including a transceiver, a transmit register, and a receiver register. The bridge logic also includes a serial bus interface with a transceiver, a transmit register, and a receiver register. Data is transmitted from the transmit register of one device to the receive register of the other device. Although the serial bus protocol limits data transfers to eight-bit segments, the I/O controller and bridge logic transmit up to twenty-four different variables by encoding each transmitted byte into a data frame that includes a two-bit frame identifier and a six-bit data field. Further, one of the data frames transmitted by the I/O controller includes an acknowledge bit to indicate when a previous frame has been received from the bridge logic.

Abstract: A computer system includes a CPU and a memory device coupled through a North bridge logic device. The computer also includes a South bridge logic device coupled to the North bridge by a primary bus. The South bridge waits as long as possible before asserting a flush request (FLUSHREQ) control signal to the North bridge. The South bridge asserts the FLUSHREQ signal to the North bridge after a peripheral device coupled to the South bridge requests access to the primary bus to run a cycle. The South bridge first flushes a write queue before asserting the FLUSHREQ signal to the North bridge. In response to the FLUSHREQ control signal, the North bridge flushes one or more of its own internal write queues in preparation for the upcoming peripheral device cycle.