Patents by Inventor Todd E. Takken

Todd E. Takken has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190141829
    Abstract: A printed circuit board (PCB) and PCB assembly. The PCB is formed of a laminate substrate of at least two layers of a non-conductive material forming at least one peripheral end face (PEF) surface separating top and bottom PCB surfaces. Embedded conductive wiring at one or more multiple layers carry energy to or from PCB surface mounted devices. The conductive wiring provides multiple conductive wire ends exposed at multiple locations along the PEF. A conductive contact structure is formed at the PEF surface to connect with one or more of the exposed conductive wire ends. One or more conductive pins are attached to the conductive contact at the PEF and are configured to mount the PCB on, and in a vertical and perpendicular orientation or a coplanar orientation relative to, a surface of a second PCB surface. The conductive pins provide one or more of: an electrical, thermal and/or mechanical contact.
    Type: Application
    Filed: November 9, 2017
    Publication date: May 9, 2019
    Inventors: Todd E. Takken, Xin Zhang, Yuan Yao, Andrew Ferencz
  • Publication number: 20190141830
    Abstract: A printed circuit board (PCB) structure and mounting assembly for joining two PCBs. A first PCB has a top and bottom surface faces and a peripheral end face separating the top and bottom surface. The first PCB has one or more conductive wire ends exposed at a surface of the peripheral end face; the exposed conductive wire ends forming multiple separate electrical contacts across the thickness and length of the PEF surface. A second PCB has a top surface face and one or more conductive pads exposed at the top surface at locations corresponding to locations of the multiple electrical contacts. A surface mount solder material is disposed on one or more exposed conductive pads for electrically connecting with corresponding the multiple electrical contacts. The disposed solder material stably joins the PEF surface of the first PCB to the top surface of the second PCB in a relative perpendicular orientation.
    Type: Application
    Filed: November 9, 2017
    Publication date: May 9, 2019
    Inventors: Todd E. Takken, Xin Zhang, Yuan Yao, Andrew Ferencz
  • Patent number: 10222125
    Abstract: An apparatus for cooling an electronic component has a planar top member of a thermal energy conductive material and a parallel planar bottom member of the material, the planar bottom member including a surface having regions configured for heat exchange contact with the electronic component. The planar top member has a plurality of stamped indent formations at a plurality of locations, each indent formation providing a contact surface such that the planar top member is affixed to the bottom member by braze or solder at each contact surface. Alternatively, the planar bottom member also has a plurality of stamped indent formations in alignment with indent formations of the top member. The planar top member is affixed to the bottom member by brazing or soldering each respective contact surface of an indent formation of the planar top member to an opposing contact surface of a corresponding indent formation of the parallel planar bottom member.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Paul W. Coteus, Shawn A. Hall, Mark D. Schultz, Todd E. Takken, Shurong Tian
  • Patent number: 10215504
    Abstract: An apparatus for cooling an electronic component has a planar top member of a thermal energy conductive material and a parallel planar bottom member of the material, the planar bottom member including a surface having regions configured for heat exchange contact with the electronic component. The joined planar top and bottom members have a sidewall structure of reduced height (and generally the height of the cold plate) between active areas in order to improve flexibility. The stiffness of the sidewalls is reduced by very advantageously reduce the height of the sidewalls. In one embodiment, the sidewalls are shorter in height corresponding to regions only between active areas. Alternatively, the sidewalls are of reduced height everywhere by insetting the active areas within the top and/or bottom sheets.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: February 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Paul W. Coteus, Shawn A. Hall, Mark D. Schultz, Todd E. Takken, Shurong Tian
  • Patent number: 10186949
    Abstract: A DC-to-DC power converter device has a common magnetic core structure that serves the functions of both transformer device and output inductor by integrating each into the common core. The transformer device has primary and secondary windings integrated into a first leg structure of the magnetic core, and the output inductor device has an output inductor winding integrated into a second leg structure of the magnetic core, the inductor winding structure for delivering output current to a load when a periodically switched input voltage is applied across the primary winding structure. The winding polarities of the transformer secondary winding structure and of the output inductor winding structure provide oppositely oriented polarities of electromotive force (EMF) to substantially reduce an output current ripple to an output load when delivering power through the transformer, through the output inductor and into the output load.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: January 22, 2019
    Assignee: International Business Machines Corporation
    Inventors: Andrew Ferencz, Todd E. Takken, Xin Zhang, Yuan Yao
  • Publication number: 20190020597
    Abstract: A structure for a network switch. The network switch may include a plurality of spine chips arranged on a plurality of spine cards, where one or more spine chips are located on each spine card; and a plurality of leaf chips arranged on a plurality of leaf cards, wherein one or more leaf chips are located on each leaf card, where each spine card is connected to every leaf chip and the plurality of spine chips are surrounded on at least two sides by leaf cards.
    Type: Application
    Filed: September 19, 2018
    Publication date: January 17, 2019
    Inventors: Paul W. Coteus, Fuad E. Doany, Shawn A. Hall, Mark D. Schultz, Todd E. Takken, Shurong Tian
  • Patent number: 10102884
    Abstract: Embodiments disclosed herein generally relate to techniques for routing data through one or more cascaded memory modules. Each memory module can include a plurality of data buffers. Each data buffer includes a plurality of ports for routing data to and/or from other memory modules. In one embodiment, the data buffer is configured to route write data to DRAM devices on a first memory module or route write data to a data buffer of at least one downstream memory module. The data buffer is also configured to receive read data from a DRAM device of the first memory module or receive read data from a downstream memory module.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: October 16, 2018
    Assignee: International Business Machines Corporation
    Inventors: Paul W. Coteus, Daniel M. Dreps, Charles A. Kilmer, Kyu-hyoun Kim, Warren E. Maule, Todd E. Takken
  • Patent number: 10097090
    Abstract: A power-delivery system may comprise a load device and a direct-current converter configured to deliver current to the load device when the direct-current converter is in an on state. The power-deliver system may comprise a voltage-measurement system configured to measure, at a beginning of each measurement cycle in a cyclic measurement pattern, a voltage at the load device. The power-deliver system may comprise a power controller configure to receive, at the beginning of each measurement cycle, the measurement of the voltage, and to perform, at the beginning of a control cycle in a cyclic control pattern, a voltage-control decision in response to a change in the measurement of the voltage being below a voltage-change threshold. The voltage-control decision may comprise whether to switch the state of the first direct-current converter. The cyclic control pattern may operate at a first frequency, and the measurement pattern may operate at a second frequency.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: October 9, 2018
    Assignee: International Business Machines Corporation
    Inventors: Andrew Ferencz, Todd E. Takken, Paul W. Coteus, Xin Zhang
  • Patent number: 10069599
    Abstract: A system and method for enabling high-speed, low-latency global collective communications among interconnected processing nodes. The global collective network optimally enables collective reduction operations to be performed during parallel algorithm operations executing in a computer structure having a plurality of the interconnected processing nodes. Router devices are included that interconnect the nodes of the network via links to facilitate performance of low-latency global processing operations at nodes of the virtual network and class structures. The global collective network may be configured to provide global barrier and interrupt functionality in asynchronous or synchronized manner. When implemented in a massively-parallel supercomputing structure, the global collective network is physically and logically partitionable according to needs of a processing algorithm.
    Type: Grant
    Filed: December 17, 2015
    Date of Patent: September 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: Matthias A. Blumrich, Paul W. Coteus, Dong Chen, Alan Gara, Mark E. Giampapa, Philip Heidelberger, Dirk Hoenicke, Todd E. Takken, Burkhard D. Steinmacher-Burow, Pavlos M. Vranas
  • Patent number: 10068886
    Abstract: A method and apparatus are provided for implementing an enhanced three dimensional (3D) semiconductor stack. A chip carrier has an aperture of a first length and first width. A first chip has at least one of a second length greater than the first length or a second width greater than the first width; a second chip attached to the first chip, the second chip having at least one of a third length less than the first length or a third width less than the first width; the first chip attached to the chip carrier by connections in an overlap region defined by at least one of the first and second lengths or the first and second widths; the second chip extending into the aperture; and a heat spreader attached to the chip carrier and in thermal contact with the first chip for dissipating heat from both the first chip and second chip.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: September 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: Paul W. Coteus, Shawn A. Hall, Todd E. Takken
  • Patent number: 9971713
    Abstract: A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: May 15, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Sameh Asaad, Ralph E. Bellofatto, Michael A. Blocksome, Matthias A. Blumrich, Peter Boyle, Jose R. Brunheroto, Dong Chen, Chen-Yong Cher, George L. Chiu, Norman Christ, Paul W. Coteus, Kristan D. Davis, Gabor J. Dozsa, Alexandre E. Eichenberger, Noel A. Eisley, Matthew R. Ellavsky, Kahn C. Evans, Bruce M. Fleischer, Thomas W. Fox, Alan Gara, Mark E. Giampapa, Thomas M. Gooding, Michael K. Gschwind, John A. Gunnels, Shawn A. Hall, Rudolf A. Haring, Philip Heidelberger, Todd A. Inglett, Brant L. Knudson, Gerard V. Kopcsay, Sameer Kumar, Amith R. Mamidala, James A. Marcella, Mark G. Megerian, Douglas R. Miller, Samuel J. Miller, Adam J. Muff, Michael B. Mundy, John K. O'Brien, Kathryn M. O'Brien, Martin Ohmacht, Jeffrey J. Parker, Ruth J. Poole, Joseph D. Ratterman, Valentina Salapura, David L. Satterfield, Robert M. Senger, Burkhard Steinmacher-Burow, William M. Stockdell, Craig B. Stunkel, Krishnan Sugavanam, Yutaka Sugawara, Todd E. Takken, Barry M. Trager, James L. Van Oosten, Charles D. Wait, Robert E. Walkup, Alfred T. Watson, Robert W. Wisniewski, Peng Wu
  • Patent number: 9922900
    Abstract: A heat source (single semiconductor chip or group of closely spaced semiconductor chips of similar height) is provided on a first side of a substrate, which substrate has on said first side a support member comprising a compressible material. A heat removal component, oriented at an angle to said heat source, is brought into proximity of said heat source such that said heat removal component contacts said support member prior to contacting said heat source. Said heat removal component is assembled to said heat source such that said support member at least partially absorbs global inequality of force that would otherwise be applied to said heat source, absent said support member comprising said compressible material.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: March 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Mark D. Schultz, Todd E. Takken, Shurong Tian, Yuan Yao
  • Patent number: 9831783
    Abstract: An apparatus includes a first circuit board including first components including a load, and a second circuit board including second components including switching power devices and an output inductor. Ground and output voltage contacts between the circuit boards are made through soldered or connectorized interfaces. Certain components on the first circuit board and certain components, including the output inductor, on the second circuit board act as a DC-DC voltage converter for the load. An output capacitance for the conversion is on the first circuit board with no board-to-board interface between the output capacitance and the load. The inductance of the board-to-board interface functions as part of the output inductor's inductance and not as a parasitic inductance. Sense components for sensing current through the output inductor are located on the first circuit board. Parasitic inductance of the board-to-board interface has less effect on a sense signal provided to a controller.
    Type: Grant
    Filed: December 30, 2015
    Date of Patent: November 28, 2017
    Assignee: International Business Machines Corporation
    Inventors: Paul W Coteus, Andrew Ferencz, Shawn A Hall, Todd E Takken, Shurong Tian, Xin Zhang
  • Patent number: 9823858
    Abstract: A method for memory management includes streaming bits to a memory buffer on a memory device using a write data channel that optimizes a speed of writing to the memory devices. The bits are written to non-volatile memory cells in the memory device at a first speed, using a bi-directional bus. Bits are read from the memory device over a read channel to provide reads at a second speed that is slower than the first speed, using the bi-directional bus.
    Type: Grant
    Filed: November 4, 2016
    Date of Patent: November 21, 2017
    Assignee: International Business Machines Corporation
    Inventors: John K. DeBrosse, Blake G. Fitch, Michele M. Franceschini, Todd E. Takken, Daniel C. Worledge
  • Patent number: 9792052
    Abstract: A memory includes multiple non-volatile memory devices, each having multiple nonvolatile memory cells. A write controller is configured to stream bits to the memory devices using a write data channel that optimizes a speed of writing to the memory devices to provide writes at a first speed. A read controller is configured to read bits from the memory devices, at a second speed slower than the first speed, using a read channel. A bi-directional bus that both the write controller and the self-referenced read controller share to access the plurality of non-volatile memory devices.
    Type: Grant
    Filed: September 22, 2016
    Date of Patent: October 17, 2017
    Assignee: International Business Machines Corporation
    Inventors: John K. Debrosse, Blake G. Fitch, Michele M. Franceschini, Todd E. Takken, Daniel C. Worledge
  • Publication number: 20170194871
    Abstract: An apparatus includes a first circuit board including first components including a load, and a second circuit board including second components including switching power devices and an output inductor. Ground and output voltage contacts between the circuit boards are made through soldered or connectorized interfaces. Certain components on the first circuit board and certain components, including the output inductor, on the second circuit board act as a DC-DC voltage converter for the load. An output capacitance for the conversion is on the first circuit board with no board-to-board interface between the output capacitance and the load. The inductance of the board-to-board interface functions as part of the output inductor's inductance and not as a parasitic inductance. Sense components for sensing current through the output inductor are located on the first circuit board. Parasitic inductance of the board-to-board interface has less effect on a sense signal provided to a controller.
    Type: Application
    Filed: December 30, 2015
    Publication date: July 6, 2017
    Inventors: Paul W. Coteus, Andrew Ferencz, Shawn A. Hall, Todd E. Takken, Shurong Tian, Xin Zhang
  • Publication number: 20170170092
    Abstract: A heat source (single semiconductor chip or group of closely spaced semiconductor chips of similar height) is provided on a first side of a substrate, which substrate has on said first side a support member comprising a compressible material. A heat removal component, oriented at an angle to said heat source, is brought into proximity of said heat source such that said heat removal component contacts said support member prior to contacting said heat source. Said heat removal component is assembled to said heat source such that said support member at least partially absorbs global inequality of force that would otherwise be applied to said heat source, absent said support member comprising said compressible material.
    Type: Application
    Filed: January 23, 2017
    Publication date: June 15, 2017
    Inventors: Mark D. Schultz, Todd E. Takken, Shurong Tian, Yuan Yao
  • Publication number: 20170155598
    Abstract: A structure for a network switch. The network switch may include a plurality of spine chips arranged on a plurality of spine cards, where one or more spine chips are located on each spine card; and a plurality of leaf chips arranged on a plurality of leaf cards, wherein one or more leaf chips are located on each leaf card, where each spine card is connected to every leaf chip and the plurality of spine chips are surrounded on at least two sides by leaf cards.
    Type: Application
    Filed: February 13, 2017
    Publication date: June 1, 2017
    Inventors: Paul W. Coteus, Fuad E. Doany, Shawn A. Hall, Mark D. Schultz, Todd E. Takken, Shurong Tian
  • Publication number: 20170115930
    Abstract: Embodiments disclosed herein generally relate to techniques for routing data through one or more cascaded memory modules. Each memory module can include a plurality of data buffers. Each data buffer includes a plurality of ports for routing data to and/or from other memory modules. In one embodiment, the data buffer is configured to route write data to DRAM devices on a first memory module or route write data to a data buffer of at least one downstream memory module. The data buffer is also configured to receive read data from a DRAM device of the first memory module or receive read data from a downstream memory module.
    Type: Application
    Filed: October 22, 2015
    Publication date: April 27, 2017
    Inventors: Paul W. COTEUS, Daniel M. DREPS, Charles A. KILMER, Kyu-hyoun KIM, Warren E. MAULE, Todd E. TAKKEN
  • Patent number: 9634959
    Abstract: A structure for a network switch. The network switch may include a plurality of spine chips arranged on a plurality of spine cards, where one or more spine chips are located on each spine card; and a plurality of leaf chips arranged on a plurality of leaf cards, wherein one or more leaf chips are located on each leaf card, where each spine card is connected to every leaf chip and the plurality of spine chips are surrounded on at least two sides by leaf cards.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: April 25, 2017
    Assignee: International Business Machines Corporation
    Inventors: Paul W. Coteus, Fuad E. Doany, Shawn A. Hall, Mark D. Schultz, Todd E. Takken, Shurong Tian