Abstract: The present disclosure relates generally to sol-gel polymer composites that comprise chitosan, a hydrophilic polymer, a polysiloxane, and a gelation agent in a suitable medium. Advantageously, the sol-gel polymer composite can form a durable seal or strong solid in response to one or more physiological stimulus. The disclosure further relates to medical and veterinary uses of the composite, particularly, methods and delivery systems for reducing or preventing the incidence of a mammary disorder in a dairy animal. More particularly, the disclosure includes methods and sol-gel polymer composite compositions for creating a physical barrier on the teat surface or in the teat canal or cistern of a non-human animal for prophylactic treatment of mammary disorders such as mastitis wherein the sol-gel polymer creates a seal in response to one or more physiological stimulus.

Abstract: The present disclosure relates generally to sol-gel polymer composites that comprise chitosan, a hydrophilic polymer, a polysiloxane, and a gelation agent in a suitable medium. Advantageously, the sol-gel polymer composite can form a durable seal or strong solid in response to one or more physiological stimulus. The disclosure further relates to medical and veterinary uses of the composite, particularly, methods and delivery systems for reducing or preventing the incidence of a mammary disorder in a dairy animal. More particularly, the disclosure includes methods and sol-gel polymer composite compositions for creating a physical barrier on the teat surface or in the teat canal or cistern of a non-human animal for prophylactic treatment of mammary disorders such as mastitis wherein the sol-gel polymer creates a seal in response to one or more physiological stimulus.

Abstract: A multi-core microprocessor has a plurality of processor cores which are coupled to a bridge element. The bridge element sends transactions to and/or receives transactions from the processor cores, where each transaction has one or more packets. The transactions include atomic transactions. The bridge element comprises a buffer unit storing a time stamp for each packet sent or received. Furthermore, a multi-core multi-node processor system is provided that has debug hardware to capture and time stamp intra-node and/or inter-node transaction packets. Atomic operations are, for example, atomic read-modify-write instructions.

Abstract: A method of operating a computer system. A first processor sends a first unit of binary information to an input/output (I/O) unit. The I/O unit then conveys the first unit of binary information to a functional unit in the computer system. A system response from the functional unit is then received by the I/O unit, which forwards the system response to the first processor. The system response is also stored in a first buffer. After a predetermined delay time has elapsed, the system response is then forwarded to the second processor.

Abstract: A multi-core multi-node processor system has a plurality of multiprocessor nodes, each including a plurality of microprocessor cores. The plurality of microprocessor nodes and cores are connected and form a transactional communication network. The multi-core multi-node processor system has further one or more buffer units collecting transaction data relating to transactions sent from one core to another core. An agent is included which calculates latency data from the collected transaction data, processes the calculated latency data to gather transaction latency coverage data, and creates random test generator templates from the gathered transaction latency coverage data. The transaction latency coverage data indicates at least the latencies of the transactions detected during collection of the transaction data having a pre-determined latency, and includes, for example, four components for transaction type latency, transaction sequence latency, transaction overlap latency, and packet distance latency.

Abstract: A multi-core microprocessor has a plurality of processor cores which are coupled to a bridge element. The bridge element sends transactions to and/or receives transactions from the processor cores, where each transaction has one or more packets. The transactions include atomic transactions. The bridge element comprises a buffer unit storing a time stamp for each packet sent or received. Furthermore, a multi-core multi-node processor system is provided that has debug hardware to capture and time stamp intra-node and/or inter-node transaction packets. Atomic operations are, for example, atomic read-modify-write instructions.

Abstract: A method and apparatus for concatenating and piggybacking data packets in a bi-directional communication device include, in response to a first transmission queue of the bi-directional communication device containing less than a threshold number of data packets, transferring a data packet from a second transmission queue in the bi-directional communication device to the first transmission queue, the transferred data packet comprising at least two concatenated data packets. The method and apparatus further include identifying the transferred data packet as a ready-to-send data packet in the first transmission queue after the transfer, and indicating the presence of a subsequent ready-to-send data packet in a primary ready-to-send data packet, the primary ready-to-send data packet and the subsequent ready-to-send data packet existing in a sequence of ready-to-send data packets in the first transmission queue.

Abstract: A method and apparatus for concatenating and piggybacking data packets in a bi-directional communication device include, in response to a first transmission queue of the bi-directional communication device containing less than a threshold number of data packets, transferring a data packet from a second transmission queue in the bi-directional communication device to the first transmission queue, the transferred data packet comprising at least two concatenated data packets. The method and apparatus further include identifying the transferred data packet as a ready-to-send data packet in the first transmission queue after the transfer, and indicating the presence of a subsequent ready-to-send data packet in a primary ready-to-send data packet, the primary ready-to-send data packet and the subsequent ready-to-send data packet existing in a sequence of ready-to-send data packets in the first transmission queue.