Patents by Inventor Todd Gandy

Todd Gandy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of forming an integrated circuit having spacer after shallow trench fill and integrated circuit formed thereby
    Patent number: 6087709
    Abstract: A method of forming an isolation region in an integrated circuit and an integrated circuit formed thereby. A method preferably includes forming at least one trench in a semiconductor substrate, forming an insulation layer of material in the at least one trench and on peripheral regions of the at least one trench of the semiconductor substrate, forming a sacrificial layer of material on the insulation layer having a different polishing rate than the insulation layer, and polishing the layer having the different polishing rate and portions of the insulation layer so that the sacrificial layer having the different polishing rate and portions of the insulation layer are removed, so that other portions of the insulation layer remain in the at least one trench of the substrate, and so that the upper surface of the at least one trench and the peripheral regions thereof in combination provide a substantially planar surface.
    Type: Grant
    Filed: August 23, 1999
    Date of Patent: July 11, 2000
    Assignee: STMicroelectronics, Inc.
    Inventors: Todd Gandy, Ronald Sampson, Robert Hodges
  • Method of forming an integrated circuit having spacer after shallow trench fill and integrated circuit formed thereby
    Patent number: 6022788
    Abstract: A method of forming an isolation region in an integrated circuit and an integrated circuit formed thereby. A method preferably includes forming at least one trench in a semiconductor substrate, forming an insulation layer of material in the at least one trench and on peripheral regions of the at least one trench of the semiconductor substrate, forming a sacrificial layer of material on the insulation layer having a different polishing rate than the insulation layer, and polishing the layer having the different polishing rate and portions of the insulation layer so that the sacrificial layer having the different polishing rate and portions of the insulation layer are removed, so that other portions of the insulation layer remain in the at least one trench of the substrate, and so that the upper surface of the at least one trench and the peripheral regions thereof in combination provide a substantially planar surface.
    Type: Grant
    Filed: December 23, 1997
    Date of Patent: February 8, 2000
    Assignee: STMicroelectronics, Inc.
    Inventors: Todd Gandy, Ronald Sampson, Robert Hodges