Abstract: A distributed switch may include a plurality of sub-switches. These sub-switches may be arranged in a hierarchy that increases the available bandwidth for transmitting multicast data frames across the switch fabric. Moreover, the distributed switch may be compatible with link aggregation where multiple physical connections are grouped together to create an aggregated (logical) link. Link aggregation requires similar data frames to use the same data path when traversing the distributed switch. With a unicast data frame, the sub-switch in the distributed switch that receives the data frame typically identifies the destination port (during a process called link selection) and forwards the data frame to the sub-switch containing that port. However, with multicast data frames, instead of the receiving sub-switch performing link selection to determine the destination port, link selection may be done by a different sub-switch or not done at all.

Abstract: A distributed switch may include a plurality of sub-switches. These sub-switches may be arranged in a hierarchy that increases the available bandwidth for transmitting multicast data frames across the switch fabric. Moreover, the distributed switch may be compatible with link aggregation where multiple physical connections are grouped together to create an aggregated (logical) link. Link aggregation requires similar data frames to use the same data path when traversing the distributed switch. With a unicast data frame, the sub-switch in the distributed switch that receives the data frame typically identifies the destination port (during a process called link selection) and forwards the data frame to the sub-switch containing that port. However, with multicast data frames, instead of the receiving sub-switch performing link selection to determine the destination port, link selection may be done by a different sub-switch or not done at all.

Abstract: Techniques are provided for multicast miss notification for a distributed network switch. In one embodiment, a bridge element in the distributed network switch receives a frame destined for a multicast group on a network. If a local multicast forwarding table of the bridge element does not include any forwarding entry for the multicast group, a forwarding entry is selected from the local multicast forwarding table as a candidate for being replaced. An indication of the candidate is sent to a management controller in the distributed network switch.

Abstract: A distributed switch may include a hierarchy with one or more levels of surrogate sub-switches (and surrogate bridge elements) that enable the distributed switch to scale bandwidth based on the size of the membership of a multicast group. When a sub-switch receives a multicast data frame, it forwards the packet to one of the surrogate sub-switches. Each surrogate sub-switch may then forward the packet to another surrogate in a different hierarchical level or to a destination computing device. Because the surrogates may transmit the data frame in parallel using two or more connection interfaces, the bandwidth used to forward the multicast packet increases for each surrogate used.

Abstract: A distributed switch may include a hierarchy with one or more levels of surrogate sub-switches (and surrogate bridge elements) that enable the distributed switch to scale bandwidth based on the size of the membership of a multicast group. When a sub-switch receives a multicast data frame, it forwards the packet to one of the surrogate sub-switches. Each surrogate sub-switch may then forward the packet to another surrogate in a different hierarchical level or to a destination computing device. Because the surrogates may transmit the data frame in parallel using two or more connection interfaces, the bandwidth used to forward the multicast packet increases for each surrogate used.

Abstract: The distributed switch may include a plurality of chips (i.e., sub-switches) on a switch module. These sub-switches may receive from a computing device connected to a Tx/Rx port a multicast data frame (e.g., an Ethernet frame) that designates a plurality of different destinations. Instead of simply using one egress connection interface to forward the copies of the data frame to each of the destinations sequentially, the sub-switch may use a plurality of a connection interfaces to transfer copies of the multicast data frame simultaneously. The port that receives the multicast data frame can borrow the connection interfaces (and associated hardware such as buffers) assigned to these other ports to transmit copies of the multicast data frame simultaneously.

Abstract: A distributed switch may include a hierarchy with one or more levels of surrogate sub-switches (and surrogate bridge elements) that enable the distributed switch to scale bandwidth based on the size of the membership of a multicast group. Moreover, each surrogate may optimize the hierarchy according to one or more optimization criteria. For example, each surrogate in the hierarchy may have the necessary information to ensure that if the next surrogate in the hierarchy is unavailable, the data may be routed to a backup surrogate. The selected hierarchy may be further optimized by skipping surrogates (or a surrogate level) such that the data intended for a skipped surrogate is sent to a surrogate in a lower-level of the hierarchy. This may better utilize the connection interfaces in the transmitting sub-switches and eliminate any unnecessary surrogate-to-surrogate transfers.

Abstract: A distributed switch may include a plurality of sub-switches. These sub-switches may be arranged in a hierarchy that increases the available bandwidth for transmitting multicast data frames across the switch fabric. Moreover, the distributed switch may be compatible with link aggregation where multiple physical connections are grouped together to create an aggregated (logical) link. Link aggregation requires similar data frames to use the same data path when traversing the distributed switch. With a unicast data frame, the sub-switch in the distributed switch that receives the data frame typically identifies the destination port (during a process called link selection) and forwards the data frame to the sub-switch containing that port. However, with multicast data frames, instead of the receiving sub-switch performing link selection to determine the destination port, link selection may be done by a different sub-switch or not done at all.

Abstract: The distributed switch may include a plurality of chips (i.e., sub-switches) on a switch module. These sub-switches may receive from a computing device connected to a Tx/Rx port a multicast data frame (e.g., an Ethernet frame) that designates a plurality of different destinations. Instead of simply using one egress connection interface to forward the copies of the data frame to each of the destinations sequentially, the sub-switch may use a plurality of a connection interfaces to transfer copies of the multicast data frame simultaneously. The port that receives the multicast data frame can borrow the connection interfaces (and associated hardware such as buffers) assigned to these other ports to transmit copies of the multicast data frame simultaneously.

Abstract: A distributed switch may include a plurality of sub-switches. These sub-switches may be arranged in a hierarchy that increases the available bandwidth for transmitting multicast data frames across the switch fabric. Moreover, the distributed switch may be compatible with link aggregation where multiple physical connections are grouped together to create an aggregated (logical) link. Link aggregation requires similar data frames to use the same data path when traversing the distributed switch. With a unicast data frame, the sub-switch in the distributed switch that receives the data frame typically identifies the destination port (during a process called link selection) and forwards the data frame to the sub-switch containing that port. However, with multicast data frames, instead of the receiving sub-switch performing link selection to determine the destination port, link selection may be done by a different sub-switch or not done at all.

Abstract: A distributed switch may include a hierarchy with one or more levels of surrogate sub-switches (and surrogate bridge elements) that enable the distributed switch to scale bandwidth based on the size of the membership of a multicast group. Moreover, each surrogate may optimize the hierarchy according to one or more optimization criteria. For example, each surrogate in the hierarchy may have the necessary information to ensure that if the next surrogate in the hierarchy is unavailable, the data may be routed to a backup surrogate. The selected hierarchy may be further optimized by skipping surrogates (or a surrogate level) such that the data intended for a skipped surrogate is sent to a surrogate in a lower-level of the hierarchy. This may better utilize the connection interfaces in the transmitting sub-switches and eliminate any unnecessary surrogate-to-surrogate transfers.

Abstract: Techniques are provided for multicast miss notification for a distributed network switch. In one embodiment, a bridge element in the distributed network switch receives a frame destined for a multicast group on a network. If a local multicast forwarding table of the bridge element does not include any forwarding entry for the multicast group, a forwarding entry is selected from the local multicast forwarding table as a candidate for being replaced. An indication of the candidate is sent to a management controller in the distributed network switch.

Abstract: Apparatuses and methods to request multicast membership information in a distributed switch are provided. A particular method may include requesting multicast membership information of a group identified by a multicast destination address in a distributed switch. The distributed switch may include a plurality of distributed switch elements with a plurality of switch forwarding units. The method may generate a miss event indicating that the multicast destination address is unregistered in a switch forwarding unit of a distributed switch element and there is a need for the multicast membership information. The method may also request the multicast membership information of the multicast destination address in response to the miss event. The method may further initiate a query for the multicast membership information of the multicast destination address in response to the request.

Abstract: A technique for accessing a memory array includes receiving, from multiple requesters, memory access requests directed to a single port of the memory array. The memory access requests associated with each of the multiple requesters are serviced, based on a priority assigned to each of the multiple requesters, while maintaining a fixed timing for the memory access requests.

Abstract: A design structure includes a data communication circuit to facilitate communication between a deserializer, responsive to a serial data stream, which puts data onto a parallel bus, and a device that is in data communication therewith. The circuit a deserialization clock that asserts a clock read pulse each time data on the parallel bus is valid. A delay unit asserts a corresponding delayed clock pulse. The delayed clock pulse is delayed from the clock read pulse by a predetermined period. A clock tree repeats the delayed clock pulse and periodically asserts a plurality of end point repeated clock pulses, each of which has a substantially simultaneous leading edge. The predetermined amount of time is selected so as to cause each of the end point repeated clock signals to be asserted when data on the parallel bus is valid, thereby enabling the device to read data from the parallel bus.

Abstract: A technique for accessing a memory array includes receiving, from multiple requesters, memory access requests directed to a single port of the memory array. The memory access requests associated with each of the multiple requesters are serviced, based on a priority assigned to each of the multiple requesters, while maintaining a fixed timing for the memory access requests.

Abstract: In a method for reading data from a serial data source in a parallel format, data from the serial data source is deserialized by placing a plurality of predefined units of data onto a parallel bus and asserting a deserialization clock when each of the plurality of predefined units is valid on the parallel bus. A delayed clock pulse is generated a predetermined amount of time after each assertion of the deserialization clock. Each delayed pulse is repeated so as to generate an end point repeated clock pulse corresponding to each delayed pulse wherein the predetermined amount of time is an amount of time that ensures that each predefined unit of data on the parallel bus is valid when each end point repeated clock pulse is asserted.

Abstract: In a method for reading data from a serial data source in a parallel format, data from the serial data source is deserialized by placing a plurality of predefined units of data onto a parallel bus and asserting a deserialization clock when each of the plurality of predefined units is valid on the parallel bus. A delayed clock pulse is generated a predetermined amount of time after each assertion of the deserialization clock. Each delayed pulse is repeated so as to generate an end point repeated clock pulse corresponding to each delayed pulse wherein the predetermined amount of time is an amount of time that ensures that each predefined unit of data on the parallel bus is valid when each end point repeated clock pulse is asserted.

Abstract: A design structure includes a data communication circuit to facilitate communication between a deserializer, responsive to a serial data stream, which puts data onto a parallel bus, and a device that is in data communication therewith. The circuit a deserialization clock that asserts a clock read pulse each time data on the parallel bus is valid. A delay unit asserts a corresponding delayed clock pulse. The delayed clock pulse is delayed from the clock read pulse by a predetermined period. A clock tree repeats the delayed clock pulse and periodically asserts a plurality of end point repeated clock pulses, each of which has a substantially simultaneous leading edge. The predetermined amount of time is selected so as to cause each of the end point repeated clock signals to be asserted when data on the parallel bus is valid, thereby enabling the device to read data from the parallel bus.

Abstract: In a method for reading data from a serial data source in a parallel format, data from the serial data source is deserialized by placing a plurality of predefined units of data onto a parallel bus and asserting a deserialization clock when each of the plurality of predefined units is valid on the parallel bus. A delayed clock pulse is generated a predetermined amount of time after each assertion of the deserialization clock. Each delayed pulse is repeated so as to generate an end point repeated clock pulse corresponding to each delayed pulse wherein the predetermined amount of time is an amount of time that ensures that each predefined unit of data on the parallel bus is valid when each end point repeated clock pulse is asserted.