Abstract: Thermal control of a multi-chip module in an operating environment is facilitated by predetermining separate thermal control points for multiple chips of the multi-chip module, with a first chip and a second chip having different predetermined thermal control points, and saving the predetermined thermal control points for reference by a thermal control of the multi-chip module in an operating environment. The thermal control monitors an operating temperature of the first chip, and compares the operating temperature of the first chip to the predetermined thermal control point of that chip. The thermal control further initiates a control action to control temperature of the first chip based on comparing the operating temperature of the first chip to the predetermined thermal control point of the first chip.

Abstract: Thermal control of a multi-chip module in an operating environment is facilitated by predetermining separate thermal control points for multiple chips of the multi-chip module, with a first chip and a second chip having different predetermined thermal control points, and saving the predetermined thermal control points for reference by a thermal control of the multi-chip module in an operating environment. The thermal control monitors an operating temperature of the first chip, and compares the operating temperature of the first chip to the predetermined thermal control point of that chip. The thermal control further initiates a control action to control temperature of the first chip based on comparing the operating temperature of the first chip to the predetermined thermal control point of the first chip.

Abstract: A system with a local data collector that collects power management data for a subsystem. The local data collector can determine whether a first formatting associated with a first channel between the local data collector and a system power management data collector is equivalent to a second formatting associated with a second channel between the local data collector and the system power management data collector, and in response to a determination that the first formatting and second formatting are not equivalent format the power management data according to the first formatting; store the power management data formatted according to the first formatting in a first location in a memory; format the power management data according to the second formatting; and store the power management data formatted according to the second formatting in a second location the memory.

Abstract: A system with a local data collector that collects power management data for a subsystem. The local data collector can determine whether a first formatting associated with a first channel between the local data collector and a system power management data collector is equivalent to a second formatting associated with a second channel between the local data collector and the system power management data collector, and in response to a determination that the first formatting and second formatting are not equivalent format the power management data according to the first formatting; store the power management data formatted according to the first formatting in a first location in a memory; format the power management data according to the second formatting; and store the power management data formatted according to the second formatting in a second location the memory.

Abstract: A system with a local data collector that collects power management data for a subsystem. The local data collector can determine whether a first formatting associated with a first channel between the local data collector and a system power management data collector is equivalent to a second formatting associated with a second channel between the local data collector and the system power management data collector, and in response to a determination that the first formatting and second formatting are not equivalent format the power management data according to the first formatting; store the power management data formatted according to the first formatting in a first location in a memory; format the power management data according to the second formatting; and store the power management data formatted according to the second formatting in a second location the memory.

Abstract: An apparatus includes a plurality of components and a plurality of component controllers. Each of the plurality of component controllers is associated with at least one component of the plurality of components. Each component controller is configured to compute a local power budget for the at least one component based, at least in part, on the power differential and the proportion of the total power consumption corresponding to the at least one component. A service processor is configured to determine failure associated with at least one component controller of the plurality of component controllers or the at least one component associated with the at least one component controller. The service processor is configured to in response to a reset threshold not being exceeded, reset the at least one component controller without interrupting operations of any components of the at least one component that have not failed.

Abstract: Component power consumption is collected from each of a plurality of controllers of a node having a plurality of components. The component power consumption is provided to each of the plurality of controllers. A power differential is determined as a difference between a power cap for an apparatus and a total power consumption for the apparatus based, at least in part, on the component power consumption. A proportion of the total power consumption corresponding to the at least one component associated with the at least one component controller is determined. A local power budget is computed for the at least one component based, at least in part, on the power differential and the proportion of the total power consumption corresponding to the at least one component. A failure associated with the at least one component controller or the at least one component is determined.

Abstract: A method, system, and computer program product for system-wide power conservation using memory cache are provided. A memory access request is received at a location in a memory architecture where processing the memory access request has to use a last level of cache before reaching a memory device holding a requested data. Using a memory controller, the memory access request is caused to wait, omitting adding the memory access request to a queue of existing memory access requests accepted for processing using the last level of cache. All the existing memory access requests in the queue are processed using the last level of cache. The last level of cache is purged to the memory device. The memory access request is processed using an alternative path to the memory device that avoids the last level of cache. A cache device used as the last level of cache is powered down.

Abstract: Component power consumption is collected from each of a plurality of controllers of a node having a plurality of components. The component power consumption is provided to each of the plurality of controllers. A power differential is determined as a difference between a power cap for an apparatus and a total power consumption for the apparatus based, at least in part, on the component power consumption. A proportion of the total power consumption corresponding to the at least one component associated with the at least one component controller is determined. A local power budget is computed for the at least one component based, at least in part, on the power differential and the proportion of the total power consumption corresponding to the at least one component. A failure associated with the at least one component controller or the at least one component is determined.

Abstract: An apparatus includes a plurality of components and a plurality of component controllers. Each of the plurality of component controllers is associated with at least one component of the plurality of components. Each component controller is configured to compute a local power budget for the at least one component based, at least in part, on the power differential and the proportion of the total power consumption corresponding to the at least one component. A service processor is configured to determine failure associated with at least one component controller of the plurality of component controllers or the at least one component associated with the at least one component controller. The service processor is configured to in response to a reset threshold not being exceeded, reset the at least one component controller without interrupting operations of any components of the at least one component that have not failed.

Abstract: A system with a local data collector that collects power management data for a subsystem. The local data collector can determine whether a first formatting associated with a first channel between the local data collector and a system power management data collector is equivalent to a second formatting associated with a second channel between the local data collector and the system power management data collector, and in response to a determination that the first formatting and second formatting are not equivalent format the power management data according to the first formatting; store the power management data formatted according to the first formatting in a first location in a memory; format the power management data according to the second formatting; and store the power management data formatted according to the second formatting in a second location the memory.

Abstract: A method, system, and computer program product for system-wide power conservation using memory cache are provided. A memory access request is received at a location in a memory architecture where processing the memory access request has to use a last level of cache before reaching a memory device holding a requested data. Using a memory controller, the memory access request is caused to wait, omitting adding the memory access request to a queue of existing memory access requests accepted for processing using the last level of cache. All the existing memory access requests in the queue are processed using the last level of cache. The last level of cache is purged to the memory device. The memory access request is processed using an alternative path to the memory device that avoids the last level of cache. A cache device used as the last level of cache is powered down.

Abstract: A method, system, and computer usable program product for improving processor performance during power supply failure are provided in the illustrative embodiments. A throttled condition of a processor is detected in a data processing system. A voltage of the electrical power being provided to the processor is reduced. The processor is un-throttled. Additionally, a frequency of electrical power being provided to the processor may also be reduced. A determination is made whether a condition that caused the throttling has been corrected. In response to the condition having been corrected, the frequency is returned to normal frequency and the voltage is returned to normal voltage. The reducing the frequency operation and reducing the voltage operation may each be performed by distinct components communicating over a data network external to the data processing system.

Abstract: A method, system, and computer usable program product for improving processor performance during power supply failure are provided in the illustrative embodiments. A throttled condition of a processor is detected in a data processing system. A voltage of the electrical power being provided to the processor is reduced. The processor is un-throttled. Additionally, a frequency of electrical power being provided to the processor may also be reduced. A determination is made whether a condition that caused the throttling has been corrected. In response to the condition having been corrected, the frequency is returned to normal frequency and the voltage is returned to normal voltage. The reducing the frequency operation and reducing the voltage operation may each be performed by distinct components communicating over a data network external to the data processing system.

Abstract: Combinations of clock frequencies, voltages, and currents at which a processor operates normally are determined. These combinations are stored to a component on which the processor is installed. Voltage identifiers are stored to a computer system in which the component is installed. The voltage identifiers are associated with combinations of the voltages and currents. A type of the computer system is also stored to the component. A first clock frequency at which the processor operates is determined that is assigned to the type of the computer system. A first voltage and a first current are selected that are assigned to the first clock frequency. A first voltage identifier is found that is assigned to the combination of the first voltage and first current, and the first voltage identifier is sent to a voltage regulator, which supplies voltage to the processor.

Abstract: Combinations of clock frequencies, voltages, and currents at which a processor operates normally are determined. These combinations are stored to a component on which the processor is installed. Voltage identifiers are stored to a computer system in which the component is installed. The voltage identifiers are associated with combinations of the voltages and currents. A type of the computer system is also stored to the component. A first clock frequency at which the processor operates is determined that is assigned to the type of the computer system. A first voltage and a first current are selected that are assigned to the first clock frequency. A first voltage identifier is found that is assigned to the combination of the first voltage and first current, and the first voltage identifier is sent to a voltage regulator, which supplies voltage to the processor.

Abstract: A concentrator and protocol converter for concentrating signals from a plurality of information circuits and coupling to a computer system control device, and for converting between at least two communications protocols. The information circuits contain vital product data (VPD) about associated devices which is used by the computer system control device.

Abstract: A plurality of information circuits are provided for a computer system. Each information circuit is associated with an element of the computer system and each stores data about the associated element of the computer system. The stored data is accessed by a control device of the computer system in order to configure predetermined operating parameters of the computer system elements.