Patents by Inventor Todd K. Maciej

Todd K. Maciej has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Reduced footprint tool for automated processing of microelectronic substrates
    Patent number: 7134827
    Abstract: The present invention provides tools and methods of processing microelectronic substrates in which the tools maintain high throughput yet have dramatically lower footprint than conventional tools. In preferred aspects, the present invention provides novel tool designs in which multiple tool functions are overlapped in the x, y, and/or z axes of the tool in novel ways.
    Type: Grant
    Filed: September 28, 2004
    Date of Patent: November 14, 2006
    Assignee: FSI International, Inc.
    Inventors: Robert E. Larson, Sean D. Simondet, David C. Zimmerman, Todd K. Maciej, Quirin W. Matthys
  • Reduced footprint tool for automated processing of microelectronic substrates
    Patent number: 6979165
    Abstract: The present invention provides tools and methods of processing microelectronic substrates in which the tools maintain high throughput yet have dramatically lower footprint than conventional tools. In preferred aspects, the present invention provides novel tool designs in which multiple tool functions are overlapped in the x, y, and/or z axes of the tool in novel ways.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: December 27, 2005
    Assignee: FSI International, Inc.
    Inventors: Robert E. Larson, Sean D. Simondet, David C. Zimmerman, Todd K. Maciej, Quirin W. Matthys
  • Edge gripping device for handling a set of semiconductor wafers in an immersion processing system
    Patent number: 6845779
    Abstract: A microelectronic substrate handling device comprising first and second support structures spaced from each other, the first support structure having a series of upper teeth defining a series of upper notches extending along a length of the first support structure and a series of lower teeth defining a series of lower notches extending along a length of the first support structure, each of the upper and lower notches opening toward the second support structure, wherein the upper and lower notches are offset from each other by a predetermined offset distance so that an edge of a microelectronic device will fit differently within the upper and lower notches of the first support structure when supported between the first and second support structures.
    Type: Grant
    Filed: November 11, 2002
    Date of Patent: January 25, 2005
    Assignee: FSI International, Inc.
    Inventors: Tim W. Herbst, Todd K. Maciej, Tracy A. Gast, Thomas J. Wagener, Kevin L. Siefering
  • Semiconductor wafer cleaning systems and methods
    Publication number: 20030098047
    Abstract: A microelectronic substrate handling device comprising first and second support structures spaced from each other, the first support structure having a series of upper teeth defining a series of upper notches extending along a length of the first support structure and a series of lower teeth defining a series of lower notches extending along a length of the first support structure, each of the upper and lower notches opening toward the second support structure, wherein the upper and lower notches are offset from each other by a predetermined offset distance so that an edge of a microelectronic device will fit differently within the upper and lower notches of the first support structure when supported between the first and second support structures.
    Type: Application
    Filed: November 11, 2002
    Publication date: May 29, 2003
    Inventors: Tim W. Herbst, Todd K. Maciej, Tracy A. Gast, Thomas J. Wagener, Kevin L. Siefering
  • Reduced footprint tool for automated processing of microelectronic substrates
    Publication number: 20030091410
    Abstract: The present invention provides tools and methods of processing microelectronic substrates in which the tools maintain high throughput yet have dramatically lower footprint than conventional tools. In preferred aspects, the present invention provides novel tool designs in which multiple tool functions are overlapped in the x, y, and/or z axes of the tool in novel ways.
    Type: Application
    Filed: November 12, 2002
    Publication date: May 15, 2003
    Inventors: Robert E. Larson, Sean D. Simondet, David C. Zimmerman, Todd K. Maciej, Quirin W. Matthys
  • Vacuum compatible water vapor and rinse process module
    Patent number: 5820692
    Abstract: A process module which can be integrated with a reduced pressure cluster tool system for semiconductor wafer processing to perform ambient or near ambient pressure reactions without requiring an intermediate buffer chamber.
    Type: Grant
    Filed: January 16, 1996
    Date of Patent: October 13, 1998
    Assignee: FSI Interntional
    Inventors: James J. Baecker, D. Scott Becker, Michael J. Foline, Todd K. Maciej