Patents by Inventor Todd M. Rimmer

Todd M. Rimmer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220210639
    Abstract: In an embodiment, at least one interface mechanism may be provided. The mechanism may permit, at least in part, at least one process allocate, at least in part, and/or configure, at least in part, at least one network-associated object. Such allocation and/or configuration, at least in part, may be in accordance with at least one parameter set that may correspond, at least in part, to at least one query issued by the at least one process via the mechanism. Many modifications are possible without departing from this embodiment.
    Type: Application
    Filed: December 10, 2021
    Publication date: June 30, 2022
    Applicant: Intel Corporation
    Inventors: William R. Magro, Todd M. Rimmer, Robert J. Woodruff, Mark S. Hefty, Sayantan Sur
  • Patent number: 11246027
    Abstract: In an embodiment, at least one interface mechanism may be provided. The mechanism may permit, at least in part, at least one process allocate, at least in part, and/or configure, at least in part, at least one network-associated object. Such allocation and/or configuration, at least in part, may be in accordance with at least one parameter set that may correspond, at least in part, to at least one query issued by the at least one process via the mechanism. Many modifications are possible without departing from this embodiment.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: February 8, 2022
    Assignee: Intel Corporation
    Inventors: William R. Magro, Todd M. Rimmer, Robert J. Woodruff, Mark S. Hefty, Sayantan Sur
  • Patent number: 10432582
    Abstract: Technologies for scalable local addressing include one or more managed network devices coupled to one or more computing nodes via high-speed fabric links. A computing node may transmit a data packet including a destination local identifier (DLID) that identifies the destination computing node. The DLID may be 32, 24, 20, or 16 bits wide. The managed network device may determine whether the DLID is within a configurable multicast address space and, if so, forward the data packet to a multicast group. The managed network device may also determine whether the DLID is within a configurable collective address space and, if so, perform a collective acceleration operation. The number of top-most bits set in a multicast mask and the number of additional top-most bits set in a collective mask may be configured. Multicast LIDs may be converted between different bit lengths. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 27, 2014
    Date of Patent: October 1, 2019
    Assignee: Intel Corporation
    Inventors: Todd M. Rimmer, Albert S. Cheng
  • Patent number: 10432586
    Abstract: Technologies for fabric security include one or more managed network devices coupled to one or more computing nodes via high-speed fabric links. A managed network device enables a port and, while enabling the port, securely determines the node type of the link partner coupled to the port. If the link partner is a computing node, management access is not allowed at the port. The managed network device may allow management access at certain predefined ports, which may be connected to one of more management nodes. Management access may be allowed for additional ports in response to management messages received from the management nodes. The managed network device may check and verify data packet headers received from a compute node at each port. The managed network device may rate-limit management messages received from a compute node at each port. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 27, 2014
    Date of Patent: October 1, 2019
    Assignee: Intel Corporation
    Inventors: Todd M. Rimmer, Thomas D. Lovett, Alberto J. Munoz
  • Patent number: 10305802
    Abstract: Method, apparatus, and systems for reliably transferring Ethernet packet data over a link layer and facilitating fabric-to-Ethernet and Ethernet-to-fabric gateway operations at matching wire speed and packet data rate. Ethernet header and payload data is extracted from Ethernet frames received at the gateway and encapsulated in fabric packets to be forwarded to a fabric endpoint hosting an entity to which the Ethernet packet is addressed. The fabric packets are divided into flits, which are bundled in groups to form link packets that are transferred over the fabric at the Link layer using a reliable transmission scheme employing implicit ACKnowledgements. At the endpoint, the fabric packet is regenerated, and the Ethernet packet data is de-encapsulated. The Ethernet frames received from and transmitted to an Ethernet network are encoded using 64b/66b encoding, having an overhead-to-data bit ratio of 1:32.
    Type: Grant
    Filed: December 31, 2016
    Date of Patent: May 28, 2019
    Assignee: Intel Corporation
    Inventors: Mark S. Birrittella, Thomas D. Lovett, Todd M. Rimmer
  • Patent number: 9979566
    Abstract: Disclosed herein are high performance systems with low latency error correction as well as related devices and methods. In some embodiments, high performance systems may include: central processing units, adapter chips, and switch chips connected via channels, each chip including link level forward error correction and link level replay, where errors at or below a threshold level are corrected by forward error correction and remaining errors are corrected using replay. In some embodiments, high performance systems may include: central processing units, adapter chips, and switch chips connected via channels, each chip including link level forward error correction, link level replay, and a multiplexer for determining which error correction technique to use based on the number of errors and an error threshold level.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: May 22, 2018
    Assignee: Intel Corporation
    Inventors: Brent R. Rothermel, Todd M. Rimmer
  • Publication number: 20180091332
    Abstract: Disclosed herein are high performance systems with low latency error correction as well as related devices and methods. In some embodiments, high performance systems may include: central processing units, adapter chips, and switch chips connected via channels, each chip including link level forward error correction and link level replay, where errors at or below a threshold level are corrected by forward error correction and remaining errors are corrected using replay. In some embodiments, high performance systems may include: central processing units, adapter chips, and switch chips connected via channels, each chip including link level forward error correction, link level replay, and a multiplexer for determining which error correction technique to use based on the number of errors and an error threshold level.
    Type: Application
    Filed: September 27, 2016
    Publication date: March 29, 2018
    Applicant: Intel Corporation
    Inventors: Brent R. Rothermel, Todd M. Rimmer
  • Publication number: 20170339103
    Abstract: Technologies for scalable local addressing include one or more managed network devices coupled to one or more computing nodes via high-speed fabric links. A computing node may transmit a data packet including a destination local identifier (DLID) that identifies the destination computing node. The DLID may be 32, 24, 20, or 16 bits wide. The managed network device may determine whether the DLID is within a configurable multicast address space and, if so, forward the data packet to a multicast group. The managed network device may also determine whether the DLID is within a configurable collective address space and, if so, perform a collective acceleration operation. The number of top-most bits set in a multicast mask and the number of additional top-most bits set in a collective mask may be configured. Multicast LIDs may be converted between different bit lengths. Other embodiments are described and claimed.
    Type: Application
    Filed: December 27, 2014
    Publication date: November 23, 2017
    Applicant: INTEL CORPORATION
    Inventors: Todd M. RIMMER, Albert S. CHENG
  • Publication number: 20170339106
    Abstract: Technologies for fabric security include one or more managed network devices coupled to one or more computing nodes via high-speed fabric links. A managed network device enables a port and, while enabling the port, securely determines the node type of the link partner coupled to the port. If the link partner is a computing node, management access is not allowed at the port. The managed network device may allow management access at certain predefined ports, which may be connected to one of more management nodes. Management access may be allowed for additional ports in response to management messages received from the management nodes. The managed network device may check and verify data packet headers received from a compute node at each port. The managed network device may rate-limit management messages received from a compute node at each port. Other embodiments are described and claimed.
    Type: Application
    Filed: December 27, 2014
    Publication date: November 23, 2017
    Applicant: INTEL CORPORATION
    Inventors: Todd M. RIMMER, Thomas D. LOVETT, Alberto J. MUNOZ
  • Publication number: 20170331743
    Abstract: Technologies for medium grained adaptive routing include one or more managed network devices coupled to one or more computing nodes via high-speed fabric links. A computing node may transmit a data packet including a destination local identifier (DLID) that identifies the destination computing node. The managed network device determines a static destination port based on the DLID, and determines whether the static destination port is congested. If congested, the managed network device determines a port group based on the DLID and selects a dynamic destination port from the port group. The port group may include two or more destination ports of the managed network device, and port groups may overlap. Port groups may be described by port masks stored in a port group table. The port groups and mappings between DLIDs and port groups may be configured by a fabric manager. Other embodiments are described and claimed.
    Type: Application
    Filed: December 27, 2014
    Publication date: November 16, 2017
    Applicant: INTEL CORPORATION
    Inventors: Todd M. RIMMER, Renae M. WEBER
  • Publication number: 20170237659
    Abstract: Method, apparatus, and systems for reliably transferring Ethernet packet data over a link layer and facilitating fabric-to-Ethernet and Ethernet-to-fabric gateway operations at matching wire speed and packet data rate. Ethernet header and payload data is extracted from Ethernet frames received at the gateway and encapsulated in fabric packets to be forwarded to a fabric endpoint hosting an entity to which the Ethernet packet is addressed. The fabric packets are divided into flits, which are bundled in groups to form link packets that are transferred over the fabric at the Link layer using a reliable transmission scheme employing implicit ACKnowledgements. At the endpoint, the fabric packet is regenerated, and the Ethernet packet data is de-encapsulated. The Ethernet frames received from and transmitted to an Ethernet network are encoded using 64b/66b encoding, having an overhead-to-data bit ratio of 1:32.
    Type: Application
    Filed: December 31, 2016
    Publication date: August 17, 2017
    Applicant: Intel Corporation
    Inventors: Mark S Birrittella, Thomas D. Lovett, Todd M. Rimmer
  • Publication number: 20170104692
    Abstract: In an embodiment, at least one interface mechanism may be provided. The mechanism may permit, at least in part, at least one process allocate, at least in part, and/or configure, at least in part, at least one network-associated object. Such allocation and/or configuration, at least in part, may be in accordance with at least one parameter set that may correspond, at least in part, to at least one query issued by the at least one process via the mechanism. Many modifications are possible without departing from this embodiment.
    Type: Application
    Filed: September 29, 2016
    Publication date: April 13, 2017
    Inventors: WILLIAM R. MAGRO, TODD M. RIMMER, ROBERT J. WOODRUFF, MARK S. HEFTY, SAYANTAN SUR
  • Patent number: 9479506
    Abstract: In an embodiment, at least one interface mechanism may be provided. The mechanism may permit, at least in part, at least one process allocate, at least in part, and/or configure, at least in part, at least one network-associated object. Such allocation and/or configuration, at least in part, may be in accordance with at least one parameter set that may correspond, at least in part, to at least one query issued by the at least one process via the mechanism. Many modifications are possible without departing from this embodiment.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: October 25, 2016
    Assignee: Intel Corporation
    Inventors: William R. Magro, Todd M. Rimmer, Robert J. Woodruff, Mark S. Hefty, Sayantan Sur
  • Publication number: 20150305006
    Abstract: In an embodiment, at least one interface mechanism may be provided. The mechanism may permit, at least in part, at least one process allocate, at least in part, and/or configure, at least in part, at least one network-associated object. Such allocation and/or configuration, at least in part, may be in accordance with at least one parameter set that may correspond, at least in part, to at least one query issued by the at least one process via the mechanism. Many modifications are possible without departing from this embodiment.
    Type: Application
    Filed: April 16, 2014
    Publication date: October 22, 2015
    Inventors: WILLIAM R. MAGRO, TODD M. RIMMER, ROBERT J. WOODRUFF, MARK S. HEFTY, SAYANTAN SUR
  • Patent number: 7876752
    Abstract: Method and system for routing a network packet received at a port within a network is provided. The method includes (a) generating an index value based on a destination identifier for the network packet; (b) generating one or more physical port numbers based on the index value generated in step (a); wherein each port number identifies a port for sending and receiving network packets; and (c) selecting one of the physical port numbers to route the network packet; wherein the port number is selected based on reaction selector signal that is generated from a partition key table based on a partition key value embedded in the network packet.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: January 25, 2011
    Assignee: QLOGIC, Corporation
    Inventors: Todd M. Rimmer, Frank R. Dropps, Thomas R. Prohofsky, Duane J. McCrory, Edward C. McGlaughlin
  • Patent number: 7822028
    Abstract: Method and system for transferring a packet in an Infiniband network is provided. The method includes configuring a connection to connect a first network device to a second network device in the Infiniband network using a first path with a packet timeout duration and a second path with a packet timeout duration, the packet timeout duration of the first path being less than the timeout duration of the second path; attempting to transfer a packet using the first path; and using the second path to transfer the packet if a number of retries using the first path exceeds a maximum number of retries for the first path.
    Type: Grant
    Filed: October 5, 2007
    Date of Patent: October 26, 2010
    Assignee: QLOGIC, Corporation
    Inventor: Todd M Rimmer
  • Patent number: 7738371
    Abstract: Method and system for sending and receiving a network packet via an inter-switch link (ISL) is provided. The method includes receiving a network packet at a network port; obtaining a destination identifier from a packet header for the network packet; generating a physical port number for routing the network packet; generating a signal indicating that an inter-switch link for the physical port number is shared by a plurality of partitions; generating a first set of virtual lanes based on a service level to virtual lane mapping scheme; generating a second set of virtual lanes based on an inter-switch link (ISL) service level to virtual lane mapping scheme; and selecting a virtual lane from the first set of virtual lanes or the second set of virtual lanes; based on a signal generated from a partition key table.
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: June 15, 2010
    Assignee: QLOGIC, Corporation
    Inventors: Todd M Rimmer, Thomas R. Prohofsky, Duane J. McCrory
  • Patent number: 5627840
    Abstract: A method and system for optimizing shift operations by reducing the computational overhead and the number of full scan path shifts associated with accessing and modifying data on a rotating scan path image are disclosed. The system further simplifies the construction of a scan path image by inserting a programmable number of leading and trailing bits around a selected string of data bits. The system manipulates and constructs a scan path image without having to shift or prepare the entire scan path image in memory. Specifically, the system comprises a master controller having a lead bypass module, a trail bypass module, a first shift module, a second shift module, a select module and a shift control module. Collectively, these modules comprise the necessary hardware for executing a plurality of shift optimization functions which include lead and trail bypass insertion, non-destructive read, field isolation, field insertion, bit order reversion, bit rotation and simultaneous read and write operation.
    Type: Grant
    Filed: September 15, 1995
    Date of Patent: May 6, 1997
    Assignee: Unisys Corp.
    Inventors: Eric K. Hundertmark, Duane J. McCrory, Todd M. Rimmer
  • Patent number: 5574730
    Abstract: Apparatus and method that incorporate bussed test access port interface into a system control interface for testing and controlling system logic boards in a manner that is fully compliant with the IEEE 1149.1 standard, while conserving system controller card signals. The apparatus incorporates six signals per interface, which includes the five standard signals as defined by IEEE 1149.1 standard plus a maintenance enable (ME) signal. Four of the standard signals, TCK, TMS, TDI and TRST* are bussed among multiple system logic boards, while the ME signals and the TDO signals are connected in a point-to-point manner between the system controller card and system logic boards. Instruction and data on the TCK, TMS, TDI, and TRST* signals are simultaneously bussed to all system logic boards. These four signals are received by each system logic board through an interface enable circuit, controlled by the ME signal line.
    Type: Grant
    Filed: January 31, 1995
    Date of Patent: November 12, 1996
    Assignee: Unisys Corporation
    Inventors: Joseph H. End, III, Todd M. Rimmer, Andrew F. Sanderson
  • Patent number: 5430845
    Abstract: A common peripheral device interface module is disclosed for use with the Unix (Unix is a trademark of AT&T) operating system which is flexible enough to support many types of disk or tape device drivers. A common disk module (CDM) is included. The CDM contains high level disk operation commands which may be used for common reference to each disk driver on the system. Routines within the CDM are accessed by the Unix system call interface through a series of operating system entry points. Additional routines are included with the pre-existing Unix operating system Disk I/O Subsystem to improve interfacing between this subsystem and the CDM. A common tape module (CTM) is used to perform high level tape operation routines. The Unix system call interface communicates with the CTM through a group of operating system entry points. Because there is no Unix operating system tape I/O subsystem, the CTM completely implements a tape I/O subsystem.
    Type: Grant
    Filed: June 17, 1992
    Date of Patent: July 4, 1995
    Assignee: Unisys Corporation
    Inventors: Todd M. Rimmer, William P. Jordan