Patents by Inventor Todd Marquart

Todd Marquart has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190354421
    Abstract: Performing a first set of scans on a memory device in a memory system with a first time interval between each scan of the first set of scans to detect errors on the memory device, determining, from performing the first set of scans, that a rate of errors being detected on the memory device is changing, and performing a second set of scans with a second time interval between each scan of the second set of scans to detect errors on the memory device, in response to determining that the rate of errors being detected on the memory device is changing, wherein the second time interval is different than the first time interval.
    Type: Application
    Filed: May 17, 2018
    Publication date: November 21, 2019
    Inventors: Kevin R. Brandt, William C. Filipiak, Michael G. McNeeley, Kishore K. Muchherla, Sampath K. Ratnam, Akira Goda, Todd A. Marquart
  • Patent number: 9269452
    Abstract: Methods and systems for determining system lifetime characteristics are described. A number of embodiments include a number of memory devices and a controller coupled to the number of memory devices. The controller can be configured to perform a number of operations on the number of memory devices using a number of trim parameters at a testing level, and determine a system lifetime characteristic based, at least partially, on the number of operations performed on the number of memory devices using the number of trim parameters at the testing level.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: February 23, 2016
    Assignee: Micron Technology, Inc.
    Inventor: Todd Marquart
  • Patent number: 9183070
    Abstract: In an embodiment, a block of memory cells is rested in response to the block of memory cells being deemed to fail. For some embodiments, a rested block may be selected for use in response to passing an operation. In other embodiments, a rested block may be rested again or may be permanently retired from further use in response to failing the operation.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: November 10, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Todd Marquart, Sampath Ratnam, Sean Eilert
  • Publication number: 20150033087
    Abstract: In an embodiment, a block of memory cells is rested in response to the block of memory cells being deemed to fail. For some embodiments, a rested block may be selected for use in response to passing an operation. In other embodiments, a rested block may be rested again or may be permanently retired from further use in response to failing the operation.
    Type: Application
    Filed: July 24, 2013
    Publication date: January 29, 2015
    Applicant: Micron Technology, Inc.
    Inventors: Todd Marquart, Sampath Ratnam, Sean Eilert
  • Publication number: 20140362647
    Abstract: The present disclosure includes methods and systems for determining system lifetime characteristics. A number of embodiments include a number of memory devices and a controller coupled to the number of memory devices. The controller can be configured to perform a number of operations on the number of memory devices using a number of trim parameters at a testing level, and determine a system lifetime characteristic based, at least partially, on the number of operations performed on the number of memory devices using the number of trim parameters at the testing level.
    Type: Application
    Filed: July 15, 2014
    Publication date: December 11, 2014
    Inventor: Todd Marquart
  • Patent number: 8854892
    Abstract: The present disclosure includes lifetime markers for memory devices. One or more embodiments include determining a read disturb value, a quantity of erase pulses, and/or a quantity of soft program pulses associated with a number of memory cells, and providing an indicator of an advance and/or retreat of the read disturb value, the quantity of erase pulses, and/or the quantity of soft program pulses relative to a lifetime marker associated with the memory cells.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: October 7, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Todd A. Marquart
  • Patent number: 8804428
    Abstract: The present disclosure includes methods and systems for determining system lifetime characteristics. A number of embodiments include a number of memory devices and a controller coupled to the number of memory devices. The controller can be configured to perform a number of operations on the number of memory devices using a number of trim parameters at a testing level, and determine a system lifetime characteristic based, at least partially, on the number of operations performed on the number of memory devices using the number of trim parameters at the testing level.
    Type: Grant
    Filed: August 16, 2011
    Date of Patent: August 12, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Todd Marquart
  • Publication number: 20130346812
    Abstract: The present disclosure relates to wear leveling memory using error rate. A number of embodiments comprise: programming data to a selected group of a number of groups of memory cells based, at least partially, on a process cycle count corresponding to the selected group; determining an error rate corresponding to the selected group; and adjusting the process cycle count corresponding to the selected group based, at least partially, on the determined error rate corresponding to the selected group.
    Type: Application
    Filed: June 22, 2012
    Publication date: December 26, 2013
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Shirish D. Bahirat, Todd A. Marquart
  • Publication number: 20130044546
    Abstract: The present disclosure includes methods and systems for determining system lifetime characteristics. A number of embodiments include a number of memory devices and a controller coupled to the number of memory devices. The controller can be configured to perform a number of operations on the number of memory devices using a number of trim parameters at a testing level, and determine a system lifetime characteristic based, at least partially, on the number of operations performed on the number of memory devices using the number of trim parameters at the testing level.
    Type: Application
    Filed: August 16, 2011
    Publication date: February 21, 2013
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Todd Marquart
  • Patent number: 8320185
    Abstract: The present disclosure includes lifetime markers for memory devices. One or more embodiments include determining a read disturb value, a quantity of erase pulses, and/or a quantity of soft program pulses associated with a number of memory cells, and providing an indicator of an advance and/or retreat of the read disturb value, the quantity of erase pulses, and/or the quantity of soft program pulses relative to a lifetime marker associated with the memory cells.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: November 27, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Todd Marquart
  • Patent number: 8199585
    Abstract: Systems and methods are disclosed for modifying soft-programming trims of a non-volatile memory device, such as a flash memory device. The soft-programming trims may be modified based on a count of erase pulses applied to memory cells of the memory device. The number of erase pulses used to erase memory cells may be indicative of accumulated charge in the memory cell. The start voltage, step size, pulse width, number of pulses, pulse ramp, ramp rate, or any other trim of the soft-programming operation may be modified in response to the number of erase pulses.
    Type: Grant
    Filed: April 4, 2011
    Date of Patent: June 12, 2012
    Assignee: Micron Technology, Inc.
    Inventor: Todd Marquart
  • Publication number: 20110242901
    Abstract: The present disclosure includes lifetime markers for memory devices. One or more embodiments include determining a read disturb value, a quantity of erase pulses, and/or a quantity of soft program pulses associated with a number of memory cells, and providing an indicator of an advance and/or retreat of the read disturb value, the quantity of erase pulses, and/or the quantity of soft program pulses relative to a lifetime marker associated with the memory cells.
    Type: Application
    Filed: March 31, 2010
    Publication date: October 6, 2011
    Applicant: MICRON TECHNOLOGY, INC.
    Inventor: Todd Marquart
  • Patent number: 8023329
    Abstract: A selected word line that is coupled to cells for programming is biased with an initial programming voltage. The unselected word lines that are adjacent to the selected word line are biased at an initial Vpass. As the quantity of program/erase cycles on the memory device increases, the programming voltage required to successfully program the cells decreases incrementally. Vpass tracks the decrease of the programming voltage.
    Type: Grant
    Filed: April 20, 2010
    Date of Patent: September 20, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Seiichi Aritome, Todd Marquart
  • Publication number: 20110182122
    Abstract: Systems and methods are disclosed for modifying soft-programming trims of a non-volatile memory device, such as a flash memory device. The soft-programming trims may be modified based on a count of erase pulses applied to memory cells of the memory device. The number of erase pulses used to erase memory cells may be indicative of accumulated charge in the memory cell. The start voltage, step size, pulse width, number of pulses, pulse ramp, ramp rate, or any other trim of the soft-programming operation may be modified in response to the number of erase pulses.
    Type: Application
    Filed: April 4, 2011
    Publication date: July 28, 2011
    Applicant: Micron Technology, Inc.
    Inventor: Todd Marquart
  • Patent number: 7952936
    Abstract: Methods and devices are disclosed, some such methods comprising applying a verify pass-through voltage to unselected select lines of the floating-gate memory array that is greater than a read pass-through voltage applied to the unselected select lines. Other methods involve utilizing a cell current for reading a value from one or more memory cells in program-verify operations that is lower than a cell current for reading the value from the one or more memory cells in read operations.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: May 31, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Andrei Mihnea, Todd Marquart, Jeffrey Kessenich
  • Patent number: 7920427
    Abstract: Systems and methods are disclosed for modifying soft-programming trims of a non-volatile memory device, such as a flash memory device. The soft-programming trims may be modified based on a count of erase pulses applied to memory cells of the memory device. The number of erase pulses used to erase memory cells may be indicative of accumulated charge in the memory cell. The start voltage, step size, pulse width, number of pulses, pulse ramp, ramp rate, or any other trim of the soft-programming operation may be modified in response to the number of erase pulses.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: April 5, 2011
    Assignee: Micron Technology, Inc.
    Inventor: Todd Marquart
  • Publication number: 20100208523
    Abstract: Systems and methods are disclosed for modifying soft-programming trims of a non-volatile memory device, such as a flash memory device. The soft-programming trims may be modified based on a count of erase pulses applied to memory cells of the memory device. The number of erase pulses used to erase memory cells may be indicative of accumulated charge in the memory cell. The start voltage, step size, pulse width, number of pulses, pulse ramp, ramp rate, or any other trim of the soft-programming operation may be modified in response to the number of erase pulses.
    Type: Application
    Filed: February 13, 2009
    Publication date: August 19, 2010
    Applicant: Micron Technology, Inc.
    Inventor: Todd Marquart
  • Publication number: 20100202210
    Abstract: A selected word line that is coupled to cells for programming is biased with an initial programming voltage. The unselected word lines that are adjacent to the selected word line are biased at an initial Vpass. As the quantity of program/erase cycles on the memory device increases, the programming voltage required to successfully program the cells decreases incrementally. Vpass tracks the decrease of the programming voltage.
    Type: Application
    Filed: April 20, 2010
    Publication date: August 12, 2010
    Inventors: Seiichi Aritome, Todd Marquart
  • Patent number: 7715234
    Abstract: A selected word line that is coupled to cells for programming is biased with an initial programming voltage. The unselected word lines that are adjacent to the selected word line are biased at an initial Vpass. As the quantity of program/erase cycles on the memory device increases, the programming voltage required to successfully program the cells decreases incrementally. Vpass tracks the decrease of the programming voltage.
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: May 11, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Seiichi Aritome, Todd Marquart
  • Publication number: 20100046303
    Abstract: Methods and devices are disclosed, some such methods comprising applying a verify pass-through voltage to unselected select lines of the floating-gate memory array that is greater than a read pass-through voltage applied to the unselected select lines. Other methods involve utilizing a cell current for reading a value from one or more memory cells in program-verify operations that is lower than a cell current for reading the value from the one or more memory cells in read operations.
    Type: Application
    Filed: October 27, 2009
    Publication date: February 25, 2010
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Andrei Mihnea, Todd Marquart, Jeffrey Kessenich