Abstract: A voltage converting apparatus is provided that includes a dynamic driver circuit and a voltage converting circuit. The dynamic driver circuit may receive a clock signal and input signals and provide a dynamic signal based on the clock signal and the input signals. The voltage converting circuit may receive the dynamic signal from the dynamic driver circuit and provide an output signal based on the received dynamic signal. The dynamic driver circuit may be powered by a first voltage source and the voltage converting circuit may be powered by a second voltage source.

Abstract: System and method of testing a packaged random access memory (RAM) redundant integrated circuit die comprising: identifying a failed element in the redundant RAM of the packaged integrated circuit die; and replacing the failed element with a redundant element in the redundant RAM of the packaged integrated circuit die.

Abstract: Systems and methods associated with cache banking are described. One exemplary system embodiment includes an array that is physically banked into multiple banks. While inputs may be provided to the banked array at a first rate, an array access may take more than one cycle at that first rate to complete. To facilitate having the banked array appear to handle the inputs at the first rate, the example system may also include a multiplexer that is operably connected to the banks and that may be configured to provide a data value associated with an earlier access to the banks from a particular bank.

Abstract: A method of testing a plurality of memory blocks of an integrated circuit in parallel, wherein each memory block comprising data bit storage cells in an array of rows and columns, and wherein each row of storage cells is addressable to store a word of data bits having a width determined by the number of columns of the array, comprises the steps of: writing test data words in parallel to the rows of the plurality of memory blocks; reading out test data words in parallel from the rows of the plurality of memory blocks to a corresponding plurality of on-chip data word comparators; presenting corresponding expected data words in parallel to the plurality of on-chip data word comparators for comparison with the read out data words of the corresponding memory blocks; concurrently comparing corresponding data bits of the read out data words and expected data words in corresponding data bit comparators to generate a column status bit for each data bit comparison; latching the column status bit of a mismatch bit compa

Abstract: Apparatus for controlling an operational test mode of a scannable latch in a test scan chain, the scannable latch comprising a scan latch and a functional latch coupled thereto, comprises: first circuit for gating a clock signal to the functional latch, the functional latch being responsive to the gated clock signal to capture operational data, the first circuit including an input for controlling the gating operations thereof; and second circuit governed by a selection signal to apply a selected one of a first signal and second signal to the input of the first circuit to control the scannable latch between controllable and observable test modes of operation.

Abstract: System and method of testing a packaged random access memory (RAM) redundant integrated circuit die comprising: identifying a failed element in the redundant RAM of the packaged integrated circuit die; and replacing the failed element with a redundant element in the redundant RAM of the packaged integrated circuit die.

Abstract: A method of testing a plurality of memory blocks of an integrated circuit in parallel, wherein each memory block comprising data bit storage cells in an array of rows and columns, and wherein each row of storage cells is addressable to store a word of data bits having a width determined by the number of columns of the array, comprises the steps of: writing test data words in parallel to the rows of the plurality of memory blocks; reading out test data words in parallel from the rows of the plurality of memory blocks to a corresponding plurality of on-chip data word comparators; presenting corresponding expected data words in parallel to the plurality of on-chip data word comparators for comparison with the read out data words of the corresponding memory blocks; concurrently comparing corresponding data bits of the read out data words and expected data words in corresponding data bit comparators to generate a column status bit for each data bit comparison; latching the column status bit of a mismatch bit compa

Abstract: An embodiment of the invention provides a circuit for reducing power in memory cells. The input of the circuit is connected to the wordline of the memory cells. When the wordline is active, the output of the circuit applies a voltage near VDD to the positive voltage supply node of the memory cells. When the wordline is inactive, the output of the circuit applies a voltage that is reduced by at least one Vt from VDD to the positive voltage supply node of the memory cells.