Abstract: Aspects of the present disclosure provide a method for regulating an integration current of a sensing amplifier. The sensing amplifier includes a first input transistor and a second input transistor, wherein a source of the first input transistor and a source of the second input transistor are coupled to a source node. The method includes pulling a current from or sourcing the current to the source node, measuring the integration current, comparing the measured integration current with a reference signal, and adjusting the current pulled from or sourced to the source node based on the comparison.

Abstract: A receiving apparatus includes a terminating network for a three-wire serial bus and a feedback circuit. Each wire of the three-wire serial bus may be coupled through a resistance to a common node of the terminating network. The feedback circuit has a first amplifier circuit having an input coupled to the common node, a comparator that receives an output of the first amplifier circuit as a first input and a reference voltage as a second input, and a second amplifier circuit responsive to an output of the comparator and configured to inject a current through the common node.

Abstract: Aspects of the present disclosure provide a method for regulating an integration current of a sensing amplifier. The sensing amplifier includes a first input transistor and a second input transistor, wherein a source of the first input transistor and a source of the second input transistor are coupled to a source node. The method includes pulling a current from or sourcing the current to the source node, measuring the integration current, comparing the measured integration current with a reference signal, and adjusting the current pulled from or sourced to the source node based on the comparison.

Abstract: A receiving apparatus includes a terminating network for a three-wire serial bus and a feedback circuit. Each wire of the three-wire serial bus may be coupled through a resistance to a common node of the terminating network. The feedback circuit has a first amplifier circuit having an input coupled to the common node, a comparator that receives an output of the first amplifier circuit as a first input and a reference voltage as a second input, and a second amplifier circuit responsive to an output of the comparator and configured to inject a current through the common node.

Abstract: A regeneration circuit includes a first inverting circuit having an input and an output, a second inverting circuit having an input and an output, a first transistor coupled to the input of the second inverting circuit, wherein a gate of the first transistor is configured to receive a first input signal, and a second transistor coupled to the input of the first inverting circuit, wherein a gate of the second transistor is configured to receive a second input signal. The regeneration circuit also includes a first switch coupled between the first transistor and the output of the first inverting circuit, wherein a control input of the first switch is configured to receive a timing signal, and a second switch coupled between the second transistor and the output of the second inverting circuit, wherein a control input of the second switch is configured to receive the timing signal.

Abstract: In certain aspects, a regenerative stage of a sense amplifier includes a first inverter having an input and an output, and a second inverter having an input and an output. The regenerative stage also includes a third inverter having an input, an output coupled to the input of the second inverter, a first supply terminal coupled to a supply rail, and a second supply terminal coupled to the output of the first inverter. The regenerative stage further includes a fourth inverter having an input, an output coupled to the input of the first inverter, a first supply terminal coupled to the supply rail, and a second supply terminal coupled to the output of the second inverter.

Abstract: Aspects of the disclosure are directed to generating a reference voltage with trim adjustment. Accordingly, a reference voltage with trim adjustment is generating which involves generating a trim current using at least one of a plurality of selectable parallel elements; inputting the trim current to parallel resistor branches to generate a first scaled voltage; and combining a first voltage with the first scaled voltage to generate the reference voltage.

Abstract: Aspects of the disclosure are directed to generating a reference voltage with trim adjustment. Accordingly, a reference voltage with trim adjustment is generating which involves generating a trim current using at least one of a plurality of selectable parallel elements; inputting the trim current to parallel resistor branches to generate a first scaled voltage; and combining a first voltage with the first scaled voltage to generate the reference voltage.

Abstract: A resistor in a pair of resistors is selectively coupled to a current source through a selection switch during the reset phase of a voltage-mode sense amplifier so that one evaluation node for the voltage-mode sense amplifier is discharged from a power supply voltage by an ohmic voltage drop across the selectively-coupled resistor to null an offset for the voltage-mode sense amplifier.

Abstract: A resistor in a pair of resistors is selectively coupled to a current source through a selection switch during the reset phase of a voltage-mode sense amplifier so that one evaluation node for the voltage-mode sense amplifier is discharged from a power supply voltage by an ohmic voltage drop across the selectively-coupled resistor to null an offset for the voltage-mode sense amplifier.

Abstract: A differential signal processing circuit includes a local common mode voltage control circuit for controlling a common mode voltage of an output differential signal generated by the differential signal processing circuit based on an external common mode control current generated by an external common mode voltage control circuit. The differential signal processing circuit, which may be configured as a variable gain amplifier (VGA) or a continuous time linear equalizer (CTLE), includes a pair of load devices, a pair of input transistors, and a pair of current source transistors coupled via separate paths between upper and lower voltage rails. The external control circuit includes a replica circuit including a replica load device, a replica input transistor, and a replica current source transistor. The external control circuit sets the replica common mode voltage to a target using a current, wherein the external common mode control current is based on that current.

Abstract: A differential signal processing circuit includes a local common mode voltage control circuit for controlling a common mode voltage of an output differential signal generated by the differential signal processing circuit based on an external common mode control current generated by an external common mode voltage control circuit. The differential signal processing circuit, which may be configured as a variable gain amplifier (VGA) or a continuous time linear equalizer (CTLE), includes a pair of load devices, a pair of input transistors, and a pair of current source transistors coupled via separate paths between upper and lower voltage rails. The external control circuit includes a replica circuit including a replica load device, a replica input transistor, and a replica current source transistor. The external control circuit sets the replica common mode voltage to a target using a current, wherein the external common mode control current is based on that current.

Abstract: A rail-to-rail sense amplifier includes a PMOS differential pair and an NMOS differential pair that are arranged in parallel with regard to a biasing network for driving a class AB output stage. The sense amplifier includes a first current differential amplifier and a second current differential amplifier for increasing the output swing while reducing power consumption.

Abstract: A low power 1-tap decision feedback equalizer (DFE) is disclosed. The DFE can include a plurality of AC-coupling networks, each having an input coupled to an output of a continuous time linear equalizer (CTLE) within an active stage of a receiver to receive a corresponding pair of differential signals of data, and an output coupled to a respective one of a plurality of data samplers to present a high frequency component of the corresponding pair of differential signals to the respective data sampler. The DFE can further include a plurality of transport paths, each transport path coupled to a respective AC-coupling network to receive the corresponding pair of differential signals. Each transport path can include one of the data sampler and an injection element to passively inject an offset into the high frequency component at an input of the respective data sampler.

Abstract: One aspect relates to a method for operating a charge pump including comparing a drain voltage of a current sink transistor of the charge pump with a drain voltage of a current reference transistor, adjusting a gate bias voltage of the current sink transistor and the current reference transistor using a first error amplifier in a direction that reduces a difference between the drain voltage of the current sink transistor and the drain voltage of the current reference transistor, comparing a common-mode voltage of a loop filter with a reference voltage, and adjusting a gate bias voltage of a current source transistor of the charge pump using a second error amplifier in a direction that reduces a difference between the common-mode voltage of the loop filter and the reference voltage, wherein the first error amplifier includes a larger number of amplifying stages than the second error amplifier.

Abstract: One aspect relates to a method for operating a charge pump including comparing a drain voltage of a current sink transistor of the charge pump with a drain voltage of a current reference transistor, adjusting a gate bias voltage of the current sink transistor and the current reference transistor using a first error amplifier in a direction that reduces a difference between the drain voltage of the current sink transistor and the drain voltage of the current reference transistor, comparing a common-mode voltage of a loop filter with a reference voltage, and adjusting a gate bias voltage of a current source transistor of the charge pump using a second error amplifier in a direction that reduces a difference between the common-mode voltage of the loop filter and the reference voltage, wherein the first error amplifier includes a larger number of amplifying stages than the second error amplifier.

Abstract: An apparatus and method for generating a temperature-compensated reference voltage are disclosed. The apparatus generates substantially equal temperature-compensated currents by controlling (through negative feedback) voltages across separate resistors through which the currents flow, respectively. Two of the temperature-compensated currents are formed by combining (e.g., summing) a complementary to absolute temperature (CTAT) current (ICTAT) and a proportional to absolute temperature (PTAT) current (IPTAT). A reference voltage VREF is produced by configuring the other the temperature-compensated current to flow through an output resistor.

Abstract: The disclosure relates to an alternating current (AC) coupling circuit including first and second capacitors having first and second input terminals configured to receive an input differential signal and generate an output differential signal at first and second output terminals of the first and second capacitors. The AC coupling circuit further includes a baseline wander correction circuit configured to make the output differential signal resistant to baseline wander due to the input differential signal including one or more time intervals of unbalanced data. The baseline wander correction circuit includes a differential difference amplifier (DDA) having a first differential input configured to receive the input differential signal, a differential output configured to generate a compensation differential signal, and a second differential input configured to receive the compensation differential signal.

Abstract: One aspect of the present disclosure relates to a method for operating a charge pump. The method includes comparing a drain voltage of a current sink transistor of the charge pump with a drain voltage of a current reference transistor, and adjusting a gate bias voltage of the current sink transistor and the current reference transistor in a direction that reduces a difference between the drain voltage of the current sink transistor and the drain voltage of the current reference transistor. The method also includes comparing a common-mode voltage of a loop filter with a reference voltage, and adjusting a gate bias voltage of a current source transistor of the charge pump in a direction that reduces a difference between the common-mode voltage of the loop filter and the reference voltage.

Abstract: In certain aspects, a method for voltage regulation includes adjusting, using a feedback circuit, a resistance of a first pass element in a direction that reduces a difference between a reference voltage and a feedback voltage, wherein the first pass element is coupled between an input and an output of a voltage regulator, and the feedback voltage is equal to or proportional to a voltage at the output of the voltage regulator. The method also includes adjusting a bias voltage of the feedback circuit in a direction that reduces the difference between the reference voltage and the feedback voltage.