Abstract: A fabric interconnect system may provide a data path between nodes and/or processing elements within an interconnection fabric. Identifiers may be assigned to particular components associated with the interconnection fabric. These identifiers may uniquely identify the particular components, and may indicate a path between a root node and a particular component. In some embodiments, the identifiers include turn counts and turn values that specify a turn-based bath from the root node to a particular component. One or more identifier acceptance rules may be used in order to determine whether a given component should accept and store a particular identifier that the component receives. For example, a lower priority identifier may be discarded in favor of a higher priority identifier.

Abstract: A method and structure(s) for providing a data path between and among nodes and processing elements within an interconnection fabric are described. More specifically, a device comprising a first circuit configured to couple between a first bus and a link is described. The circuit may be configured to operate as a bridge, support PCI configuration cycles, send outgoing information serially through the link in a format different from that of the first bus, and allow a host processor, communicating through the first bus, to selectively address one or more remote devices to which the device is configured to allow access. In some embodiments, the first circuit may support “spoof-proof” data protocols, and the device may operate in multiple modes including root bridge, leaf bridge, and gateway mode. Multiple addressing models may also be used.

Abstract: A method and structure(s) for providing a data path between and among nodes and processing elements within an interconnection fabric are described. More specifically, a device comprising a first circuit configured to couple between a first bus and a link is described. The circuit may be configured to operate as a bridge, support PCI configuration cycles, send outgoing information serially through the link in a format different from that of the first bus, and allow a host processor, communicating through the first bus, to selectively address one or more remote devices to which the device is configured to allow access. In some embodiments, the first circuit may support “spoof-proof” data protocols, and the device may operate in multiple modes including root bridge, leaf bridge, and gateway mode. Multiple addressing models may also be used.

Abstract: The present invention relates generally to a generic fabric interconnect system and method for providing a data path between and among nodes and processing elements within an interconnection fabric.

Abstract: The present invention provides a system and method for encapsulating protocols across a switching fabric network. Packets, which may utilize any underlying protocol, are encapsulated with a route header. This route header contains path routing, traffic and packet size information. A novel path routing scheme is used to route packets across the fabric, where the fabric has a plurality of switches, each having a plurality of ports. Each switch uses only data from within the packet and its own port count to determine the appropriate output port. There is no need to node or address lookup mechanisms in the switches.

Abstract: The present invention relates generally to a generic fabric interconnect system and method for providing a data path between and among nodes and processing elements within an interconnection fabric.

Abstract: A system and method for routing data elements from an origin to a terminus is disclosed. The switches each have a plurality of ports. These ports are numbered relative to one another, such that a first output port, adjacent to the input port, may be numbered “0”, while a second output port, adjacent to the first output port, would be numbered “1”, This numbering continues for each port in the switch. When a data element is received on an input port of the switch, an output port is selected based on a value contained in that received data element. In one embodiment, the value is contained within a path specification, which includes a count field and a plurality of turn fields.

Abstract: A method for accessing a configuration space of a device is described. The method includes setting a first field of a packet to a value to specify a destination device, and setting a second field of the packet to a defined value to indicate that the packet is a configuration access packet. The method further includes setting a third field of the configuration access packet to a value to select one of a plurality of configuration apertures of a configuration space of the destination device, and setting a fourth field of the configuration access packet to a value to address a specific memory location within the selected aperture.

Abstract: A queuing mechanism is described for managing packets between agents of a computer system. The queuing mechanism includes an ordered queue including a plurality of queue registers to store a plurality of packets. The queuing mechanism also includes a bypass queue coupled to the ordered queue, wherein, if a packet at head of the ordered queue is a delayed request and is stalled for lack of flow control credit, then the stalled packet is moved into the bypass queue.

Abstract: The present invention relates generally to a generic fabric interconnect system and method for providing a data path between and among nodes and processing elements within an interconnection fabric.

Abstract: A system and method for selecting a fabric master using an announce phase and a own phase. During an announce phase a candidate master interrogates its Node Path Identifier to ensure that it has not already surrendered ownership to another node. If the candidate master has won the election, it then broadcasts its EUI with an indication that it is the new fabric master.

Abstract: The present invention relates generally to a generic fabric interconnect system and method for providing a data path between and among nodes and processing elements within an interconnection fabric.

Abstract: The present invention relates generally to a generic fabric interconnect system and method for providing a data path between and among nodes and processing elements within an interconnection fabric.

Abstract: A system and method for selecting a fabric master using an announce phase and a own phase. During an announce phase a candidate master interrogates its Node Path Identifier to ensure that it has not already surrendered ownership to another node. If the candidate master has won the election, it then broadcasts its EUI with an indication that it is the new fabric master.

Abstract: The present invention provides a system and method for encapsulating protocols across a switching fabric network.

Abstract: The present invention relates generally to a generic fabric interconnect system and method for providing a data path between and among nodes and processing elements within an interconnection fabric.

Abstract: A graphics subsystem (10) employs an image memory (12) that includes an on-screen part (44) and an off-screen part (46). The locations of the on-screen memory (44) are continually scanned to provide data to be displayed on a display device (16). The off-screen part (46) stores data that represent image segments that have been occluded by windowing. To transfer data between the on-screen part (44) and the off-screen part (46), an address generator (24) generates a sequence of two-dimensional addresses representing the two-dimensional positions of the pixels whose data are to be transferred. These addresses are converted to one-dimensional addresses by a simple circuit consisting of multiplexers (26 and 28), adders (30 and 32) and a multiplier (34).

Abstract: A data collection terminal includes a microprocessor, a memory and a number of devices coupled to a system bus. An interrupt controller processes the device interrupt requests by sending a vector address out on the system bus to enable the microprocessor to branch to a microprogram to process the interrupt request. Apparatus is provided to receive the vector address to generate an interrupt clear signal for those interrupts which are transitory in nature. Typical examples are a document being inserted in a device or a card seated in a device.

Abstract: A data collection terminal includes a microprocessor, a memory and a number of devices coupled to a system bus. Included among the devices is a communication controller. An interrupt controller processes the device interrupt requests by sending out a vector address to the microprocessor. This enables the microprocessor to branch to a subroutine to process the interrupt. Apparatus is provided to enable the communication controller to generate vector addresses when it sends an interrupt request to the interrupt controller.