Abstract: A system for communicating vehicle diagnostic information includes a transmitter provided in a vehicle and configured to wirelessly transmit signals according to a Bluetooth protocol. The signals transmitted are representative of vehicle diagnostic information.

Abstract: A system for communicating information facilitates wireless communication between electronic devices. The system includes a trainable transceiver provided in a vehicle. The trainable transceiver wirelessly communicates with an electronic device located external to the transceiver.

Abstract: A system for communicating information is described. The system comprises a radio frequency (RF) transceiver coupled to a vehicle. The transceiver is configured to communicate with a personal digital assistant (PDA) located external to the transceiver using wireless RF signals to transmit information between the transceiver and the PDA.

Abstract: A system for communicating information includes a transceiver provided within a vehicle that is configured for wireless communication with a cellular phone and with a portable computing device. The wireless communication between the transceiver and the cellular phone utilizes a Bluetooth communications protocol.

Abstract: A system for communicating information facilitates wireless communication between electronic devices. The system includes a transceiver provided in a vehicle. The transceiver communicates with an electronic device located external to the transceiver using a Bluetooth communications standard.

Abstract: A computer system has a memory and has a processor coupled to the memory, the processor having an access control arrangement for delaying completion of a memory access until the occurrence of a control signal. A deterministic circuit coupled to the-processor and the memory has a register arrangement containing control information loaded by the processor, the deterministic circuit having a signal generation arrangement for generating the control signal. The signal generating arrangement includes a selective delay arrangement which can selectively delay generation of the control signal during an access to the memory by a time interval having a duration which is a function of the control information in the register arrangement.

Abstract: A control circuit inhibits the CLOCK input to the CPU during power-up to prevent newer submicron CPUs from locking up during a power-up condition. The control circuit also provides a delayed control signal representing that the power supply has stabilized. This delayed control signal is used to consistently control the RESET signal.

Abstract: A computer system includes a control circuit having a request input, and a pair of connectors which are electrically coupled to the control circuit and are each connected to the request input of the control circuit, each connector being capable of removably receiving a circuit card. The control circuit includes a checking arrangement for detecting a condition in which the connectors each have therein a card having a request output controlling the request input of the control circuit.

Abstract: A system includes a system bus having data lines, an acknowledge line, an enable line, and a control line, a data storage device, a controller circuit, and an arrangement coupling the system bus, controller circuit and data storage device. The system bus can carry out a data transfer cycle in which the acknowledge, enable and control lines are actuated and the controller obtains and checks data from the data storage device and supplies it to data lines of the bus, and a verify cycle in which the acknowledge and enable lines are actuated and the control line is deactuated and the controller obtains and checks data from the storage device but does not supply it to the bus. The controller circuit is capable of operating in different modes, in one of which it forcibly sets a false error indication in response to the verify cycle.

Abstract: A memory system includes a memory unit with plural addressable storage locations, a connector arrangement for detachably electrically coupling the memory unit to a computer, and a decoding arrangement for determining whether a computer memory address is within a range of addresses to which the memory unit is to respond, the decoding arrangement including a base address register storing a value representing the first address in the range and a size register defining the number of addresses in the range.