Patents by Inventor Todd S. Kaplan

Todd S. Kaplan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7620529
    Abstract: The present invention comprises a method, an apparatus, and a computer program product for simulating a mixed-signal system. The invention comprises a first operation of generating a matrix-based wavelet operator representation of equations characterizing a system, with the matrix-based wavelet operator representation including wavelet connection coefficients. A second operation is performed by selecting a number of wavelets and a set of wavelet basis functions with which to represent a performance of the system, whereby the wavelet operator, the number of wavelets and the set of wavelet basis functions represent a wavelet model of the system. A third operation is performed by iteratively applying the wavelet model over a series of clock cycles to develop a behavioral model of the system. The invention has particular use in the area of computer-aided design and may be applied to any suitable system, whether electrical, mechanical, or other.
    Type: Grant
    Filed: October 14, 2003
    Date of Patent: November 17, 2009
    Assignees: HLR Laboratories, Aerospace Corporation
    Inventors: George C. Valley, Peter Petre, Shubha Kadambe, Todd S. Kaplan
  • Patent number: 7034728
    Abstract: A delta-sigma modulator. The novel delta-sigma modulator includes one or more filter stages arranged in cascade, wherein each filter stage includes a first circuit for generating a first output signal and second circuit for generating a second output signal; and a summing circuit for adding the first and second output signals from each of the filter stages. In an illustrative embodiment, the first circuit is a bandpass filter including an inductive-capacitive resonator and the second circuit is an integrator, which generates a second output signal that is orthogonal to the first output signal. The output of the summing circuit is digitized and then converted back to analog to provide a feedback signal. The feedback signal is subtracted from an input signal, and the resultant difference signal is input to a first filter stage.
    Type: Grant
    Filed: August 11, 2004
    Date of Patent: April 25, 2006
    Assignee: Raytheon Company
    Inventors: Louis Luh, Todd S. Kaplan
  • Publication number: 20040172226
    Abstract: The present invention comprises a method, an apparatus, and a computer program product for simulating a mixed-signal system. The invention comprises a first operation of generating a matrix-based wavelet operator representation of equations characterizing a system, with the matrix-based wavelet operator representation including wavelet connection coefficients. A second operation is performed by selecting a number of wavelets and a set of wavelet basis functions with which to represent a performance of the system, whereby the wavelet operator, the number of wavelets and the set of wavelet basis functions represent a wavelet model of the system. A third operation is performed by iteratively applying the wavelet model over a series of clock cycles to develop a behavioral model of the system. The invention has particular use in the area of computer-aided design and may be applied to any suitable system, whether electrical, mechanical, or other.
    Type: Application
    Filed: October 14, 2003
    Publication date: September 2, 2004
    Inventors: George C. Valley, Peter Petre, Shubha Kadambe, Todd S. Kaplan
  • Patent number: 6165892
    Abstract: A method for forming a planarized thin film dielectric film on a surface of a common circuit base upon which one or more integrated circuits are to be attached. The common circuit base includes raised features formed over its surface such that the raised features define a trench area between them. The method includes the steps of forming a first layer of the dielectric film over the common circuit base and over the raised features and the trench, then patterning the newly formed layer to remove portions of the layer formed over the raised features and expose the raised features. After the layer is patterned, formation of the dielectric film is completed by forming a second layer of the dielectric film over the patterned first layer.
    Type: Grant
    Filed: July 31, 1998
    Date of Patent: December 26, 2000
    Assignee: Kulicke & Soffa Holdings, Inc.
    Inventors: David J. Chazan, Ted T. Chen, Todd S. Kaplan, James L. Lykins, Michael P. Skinner, Jan I. Strandberg