Patents by Inventor Todd Strope

Todd Strope has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • System and method of matching data rates
    Patent number: 9201790
    Abstract: The present disclosure is directed to systems and methods of matching data rates. In a particular embodiment, a device includes a first data bus and a controller having a first output coupled to the first data bus to provide data to the first data bus. The device also includes a first memory of a first type coupled to the first data bus. The first memory may have a first input to receive data from the controller via the first data bus. The device also includes logic coupled to the first data bus. The logic may have a second input coupled to the first data bus to receive data from the controller via the first data bus. The device may also include a second data bus coupled to the logic. The logic may have a second output coupled to the second data bus to provide data to the second data bus. The logic may also include a second memory of a second type coupled to the second data bus. The second memory may have a third input to selectively receive data from the logic via the second data bus.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: December 1, 2015
    Assignee: Seagate Technology LLC
    Inventors: Stanton MacDonough Keeler, Todd Strope
  • SYSTEM AND METHOD OF MATCHING DATA RATES
    Publication number: 20090094389
    Abstract: The present disclosure is directed to systems and methods of matching data rates. In a particular embodiment, a device includes a first data bus and a controller having a first output coupled to the first data bus to provide data to the first data bus. The device also includes a first memory of a first type coupled to the first data bus. The first memory may have a first input to receive data from the controller via the first data bus. The device also includes logic coupled to the first data bus. The logic may have a second input coupled to the first data bus to receive data from the controller via the first data bus. The device may also include a second data bus coupled to the logic. The logic may have a second output coupled to the second data bus to provide data to the second data bus. The logic may also include a second memory of a second type coupled to the second data bus. The second memory may have a third input to selectively receive data from the logic via the second data bus.
    Type: Application
    Filed: October 9, 2007
    Publication date: April 9, 2009
    Applicant: SEAGATE TECHNOLOGY, LLC
    Inventors: Stanton MacDonough Keeler, Todd Strope