Abstract: An inductor includes a conductor having a first end and a second end, wherein the first end, the second end, or both ends are configured to be mounted on a substrate and configured to receive a heat flow; and one or more magnetic cores surrounding a first portion of the conductor, the first portion of the conductor being intermediate the first end and the second end of the conductor. A second portion of the conductor not surrounded by the one or more magnetic cores is configured to transfer the heat flow from the conductor.

Abstract: Circuits and methods are provided for utilizing decoupling capacitors to mitigate voltage droop on power supply lines of a power distribution network. A power supply line is capacitively decoupled using a first decoupling capacitor connected to the power supply line and charged to a first voltage level of the power supply line. A second decoupling capacitor is pre-charged to a second voltage level greater than the first voltage level and held in standby. A control circuit determines or predicts an occurrence of a droop event in which the first voltage decreases to a level which is at or below a droop threshold voltage level, and selectively connects the pre-charged second decoupling capacitor to the power supply line to source additional boosting current through discharging of the second decoupling capacitor and thereby capacitively decouple the power supply line using the higher second voltage and additional boosting current.

Abstract: An apparatus is provided including a transformer including a first printed circuit board having one or more conducting layers, the one or more conducting layers forming, at least in part, a transformer coil; at least one inductor; and at least one continuous piece of conducting material external to the printed circuit board, where the at least one continuous piece of conducting material forms a connection between the transformer and the at least one inductor. A method is also provided for assembling a switched-mode power supply.

Abstract: An inductor includes a conductor having a first end and a second end, wherein the first end, the second end, or both ends are configured to be mounted on a substrate and configured to receive a heat flow; and one or more magnetic cores surrounding a first portion of the conductor, the first portion of the conductor being intermediate the first end and the second end of the conductor. A second portion of the conductor not surrounded by the one or more magnetic cores is configured to transfer the heat flow from the conductor.

Abstract: Circuits and methods are provided for utilizing decoupling capacitors to mitigate voltage droop on power supply lines of a power distribution network. A power supply line is capacitively decoupled using a first decoupling capacitor connected to the power supply line and charged to a first voltage level of the power supply line. A second decoupling capacitor is pre-charged to a second voltage level greater than the first voltage level and held in standby. A control circuit determines or predicts an occurrence of a droop event in which the first voltage decreases to a level which is at or below a droop threshold voltage level, and selectively connects the pre-charged second decoupling capacitor to the power supply line to source additional boosting current through discharging of the second decoupling capacitor and thereby capacitively decouple the power supply line using the higher second voltage and additional boosting current.

Abstract: An apparatus is provided including a transformer including a first printed circuit board having one or more conducting layers, the one or more conducting layers forming, at least in part, a transformer coil; at least one inductor; and at least one continuous piece of conducting material external to the printed circuit board, where the at least one continuous piece of conducting material forms a connection between the transformer and the at least one inductor. A method is also provided for assembling a switched-mode power supply.

Abstract: An error-recovery method to enable error-free message transfer between nodes of a computer network. A first node of the network sends a packet to a second node of the network over a link between the nodes, and the first node keeps a copy of the packet on a sending end of the link until the first node receives acknowledgment from the second node that the packet was received without error. The second node tests the packet to determine if the packet is error free. If the packet is not error free, the second node sets a flag to mark the packet as corrupt. The second node returns acknowledgement to the first node specifying whether the packet was received with or without error. When the packet is received with error, the link is returned to a known state and the packet is sent again to the second node.

Abstract: Persistent data storage is provided by a computer program product that includes computer program code configured for receiving a low latency store command that includes write data. The write data is written to a first memory device that is implemented by a nonvolatile solid-state memory technology characterized by a first access speed. It is acknowledged that the write data has been successfully written to the first memory device. The write data is written to a second memory device that is implemented by a volatile memory technology. At least a portion of the data in the first memory device is written to a third memory device when a predetermined amount of data has been accumulated in the first memory device. The third memory device is implemented by a nonvolatile solid-state memory technology characterized by a second access speed that is slower than the first access speed.

Abstract: Persistent data storage with low latency is provided by a computer program product that includes computer program code configured for receiving a low latency store command that includes write data. The write data is written to a first memory device that is implemented by a nonvolatile solid-state memory technology characterized by a first access speed. It is acknowledged that the write data has been successfully written to the first memory device. The write data is written to a second memory device that is implemented by a volatile memory technology. At least a portion of the data in the first memory device is written to a third memory device when a predetermined amount of data has been accumulated in the first memory device. The third memory device is implemented by a nonvolatile solid-state memory technology characterized by a second access speed that is slower than the first access speed.

Abstract: A system and method for enabling high-speed, low-latency global collective communications among interconnected processing nodes. The global collective network optimally enables collective reduction operations to be performed during parallel algorithm operations executing in a computer structure having a plurality of the interconnected processing nodes. Router devices are included that interconnect the nodes of the network via links to facilitate performance of low-latency global processing operations at nodes of the virtual network and class structures. The global collective network may be configured to provide global barrier and interrupt functionality in asynchronous or synchronized manner. When implemented in a massively-parallel supercomputing structure, the global collective network is physically and logically partitionable according to needs of a processing algorithm.

Abstract: A tall mezzanine connector which connects the substantial middle half of each of a pair of circuit cards positioned normal thereto in such a way that there is compliance when the two halves of the circuit cards are not in alignment. The mezzanine connector comprises a header and a receptacle that includes wafers having electrical contact means at each end thereof for contacting contacts in the respective circuit cards, the wafers being held in place by an upper base member and a lower base member.

Abstract: A tall mezzanine connector which connects the substantial middle half of each of a pair of circuit cards positioned normal thereto. The mezzanine connector comprises a and a receptacle that includes wafers having electrical contact means at each end thereof for contacting contacts in the respective circuit cards, the wafers being held in place by an upper base member and a lower base member.

Abstract: A tall mezzanine connector which connects the substantial middle half of each of a pair of circuit cards positioned normal thereto in such a way that there is compliance when the two halves of the circuit cards are not in alignment. The mezzanine connector comprises a header and a receptacle that includes wafers having electrical contact means at each end thereof for contacting contacts in the respective circuit cards, the wafers being held in place by an upper base member and a lower base member.

Abstract: A method and system are disclosed for detecting memory chip failure in a computer memory system. The method comprises the steps of accessing user data from a set of user data chips, and testing the user data for errors using data from a set of system data chips. This testing is done by generating a sequence of check symbols from the user data, grouping the user data into a sequence of data symbols, and computing a specified sequence of syndromes. If all the syndromes are zero, the user data has no errors. If one of the syndromes is non-zero, then a set of discriminator expressions are computed, and used to determine whether a single or double symbol error has occurred. In the preferred embodiment, less than two full system data chips are used for testing and correcting the user data.

Abstract: An apparatus and method for controlling power usage in a computer includes a plurality of computers communicating with a local control device, and a power source supplying power to the local control device and the computer. A plurality of sensors communicate with the computer for ascertaining power usage of the computer, and a system control device communicates with the computer for controlling power usage of the computer.

Abstract: A memory system is disclosed which is comprised of a memory controller and addressable memory devices such as DRAMs. The invention provides a programmable register to control the high vs. low drive state of each bit of a memory system address and control bus during periods of bus inactivity. In this way, termination voltage supply current can be minimized, while permitting selected bus bits to be driven to a required state. This minimizes termination power dissipation while not affecting memory system performance. The technique can be extended to work for other high-speed busses as well.

Abstract: A massively parallel supercomputer of petaOPS-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC) having up to four processing elements. The ASIC nodes are interconnected by multiple independent networks that optimally maximize the throughput of packet communications between nodes with minimal latency. The multiple networks may include three high-speed networks for parallel algorithm message passing including a Torus, collective network, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. The use of a DMA engine is provided to facilitate message passing among the nodes without the expenditure of processing resources at the node.

Abstract: An apparatus and method for controlling power usage in a computer includes a plurality of computers communicating with a local control device, and a power source supplying power to the local control device and the computer. A plurality of sensors communicate with the computer for ascertaining power usage of the computer, and a system control device communicates with the computer for controlling power usage of the computer.

Abstract: A novel massively parallel supercomputer of petaOPS-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC) having up to four processing elements. The ASIC nodes are interconnected by multiple independent networks that optimally maximize the throughput of packet communications between nodes with minimal latency. The multiple networks may include three high-speed networks for parallel algorithm message passing including a Torus, collective network, and a Global Asynchronous network that provides global barrier and notification functions. These multiple independent networks may be collaboratively or independently utilized according to the needs or phases of an algorithm for optimizing algorithm processing performance. Novel use of a DMA engine is provided to facilitate message passing among the nodes without the expenditure of processing resources at the node.

Abstract: A memory system is disclosed which is comprised of a memory controller and addressable memory devices such as DRAMs. The invention provides a programmable register to control the high vs. low drive state of each bit of a memory system address and control bus during periods of bus inactivity. In this way, termination voltage supply current can be minimized, while permitting selected bus bits to be driven to a required state. This minimizes termination power dissipation while not affecting memory system performance. The technique can be extended to work for other high-speed busses as well.