Abstract: A method receives a complex instruction comprising a first portion and a second portion. The method sets a single issue queue slot and allocates an execution unit for the complex instruction, and identifies dependencies in the first and second portions. The method sets a dependency matrix slot and a consumers table slot for the first and section portion. In the event the first portion dependencies have been satisfied, the method issues the first portion and then issues the second portion from the single issue queue slot. In the event the second portion dependencies have not been satisfied, the method places the second portion into a side issue queue. The method issues the second portion when the side issue queue indicates that the second portion is eligible for issue.

Abstract: A system for using complex branch execution hardware and a hardware based Multiplex (MUX) to multiplex a fetch address of a future branch and a branch fetch address to one index hash value used to index a branch target prediction table for execution by a processor core, to reduce branch mis-prediction by preloading.

Abstract: A method for implementing speculative clock gating of digital logic circuits in a multiple stage pipeline design includes generating, in a first pipeline stage n, a valid control signal that is input to a first register in a second pipeline stage n+1, the valid control signal indicative of when an operation is qualified to be performed by the second pipeline stage n+1; and generating, in the first pipeline stage, a speculative valid control signal that is used to gate a clock signal to a plurality of additional registers in the second pipeline stage, wherein the speculative valid control signal is generated using only a subset of a total number of control inputs used in generating the valid control signal, and wherein the clock signal is sent directly, without gating, to the first register in the second pipeline stage.

Abstract: A design structure embodied in a machine readable medium used in a design process includes an apparatus for implementing speculative clock gating of digital logic circuits, including operation valid logic configured to generate, in a first pipeline stage n, a valid control signal that is input to a first register in a second pipeline stage n+1, the valid control signal indicative of when an operation is qualified to be performed by the second pipeline stage n+1; and speculative valid logic configured to generate, in the first pipeline stage, a speculative valid control signal that is used to gate a clock signal to a plurality of additional registers in the second pipeline stage, wherein the speculative valid control signal is generated using only a subset of a total number of control inputs used in generating the valid control signal, and wherein the clock signal is sent directly to the first register.

Abstract: A system and method for issuing load-dependent instructions from an issue queue in a processing unit in a data processing system. In response to a LSU determining that a load request from a load instruction missed a first level in a memory hierarchy, a LMQ allocates a load-miss queue entry corresponding to the load instruction. The LMQ associates at least one instruction dependent on the load request with the load-miss queue entry. Once data associated with the load request is retrieved, the LMQ selects at least one instruction dependent on the load request for execution on the next cycle. At least one instruction dependent on the load request is executed and a result is outputted.

Abstract: A design structure for resolving the occurrence of livelock at the interface between the processor core and memory subsystem controller. Livelock is resolved by introducing a livelock detection mechanism (which includes livelock detection utility or logic) within the processor to detect a livelock condition and dynamically change the duration of the delay stage(s) in order to alter the “harmonic” fixed-cycle loop behavior. The livelock detection logic (LDL) counts the number of flushes a particular instruction takes or the number of times an instruction re-issues without completing. The LDL then compares that number to a preset threshold number. Based on the result of the comparison, the LDL triggers the implementation of one of two different livelock resolution processes.

Abstract: A method, apparatus, and computer instructions for analyzing data from a crash of the data processing system. A portion of the memory in the data processing system is preserved in response to the crash of the data processing system. The data processing system is rebooted with an environment suited for analyzing trace data in the portion of the memory.

Abstract: A method for resolving the occurrence of livelock at the interface between the processor core and memory subsystem controller. Livelock is resolved by introducing a livelock detection mechanism (which includes livelock detection utility or logic) within the processor to detect a livelock condition and dynamically change the duration of the delay stage(s) in order to alter the “harmonic” fixed-cycle loop behavior. The livelock detection logic (LDL) counts the number of flushes a particular instruction takes or the number of times an instruction re-issues without completing. The LDL then compares that number to a preset threshold number. Based on the result of the comparison, the LDL triggers the implementation of one of two different livelock resolution processes.

Abstract: A method, apparatus, and computer instructions for monitoring a device in a data processing system. A register associated the device is accessed from a reduced function processor core through a connection between the register for the device and the reduced function processor core. The device is monitored using the value of the register.

Abstract: A method, apparatus and computer instructions for interfacing with an operating system on a data processing system. Registers in a processor are allocated for use in providing a low-level console interface to a remote data processing system, wherein the registers are accessed by the remote data processing system using the low-level console interface. Data is exchanged with the remote data processing system through the low-level console interface. Also, multiple channels may be multiplexed through this low-level console interface.

Abstract: A method, apparatus, and computer instructions for analyzing data from a crash of the data processing system. A portion of the memory in the data processing system is preserved in response to the crash of the data processing system. The data processing system is rebooted with an environment suited for analyzing trace data in the portion of the memory.

Abstract: A method, apparatus, and computer instructions for routing data in a data processing system. Registers in a processor in the data processing system are configured to route memory requests to a local input/output controller rather than a local memory controller in the data processing system. Responsive to receiving the memory request at the input/output controller, the memory request is sent to a remote input/output controller located in a remote data processing system. The remote input/output controller sends the memory request to a remote memory controller in the remote data processing system to access remote memory in the remote data processing system.

Abstract: A method, apparatus and computer instructions for discovering hardware nodes having a hierarchical organization. A subset of the hardware nodes in the data processing system is initialized prior to loading an operating system supporting parallel threads. In response to loading the operating system, thread for each hardware node discovered below a known hardware node is created to form a set of threads.