Patents by Inventor Todd W. Davies

Todd W. Davies has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080127485
    Abstract: A method for forming an electrical structure. A dielectric substrate having a metal signal line therein is provided. A first metal voltage plane is laminated to a first surface of the dielectric substrate. An opening in the first metal voltage plane is formed such that a first electrically conductive strip across the opening includes an image of a first portion of the metal signal line, wherein the image of the first portion of the metal signal line projects across the opening in the first metal voltage plane. A signal current is flowed through the metal signal line, wherein the signal current is an alternating current. A return current is flowed through the first electrically conductive strip, wherein the return current includes a portion of the signal current.
    Type: Application
    Filed: January 3, 2008
    Publication date: June 5, 2008
    Inventors: Timothy W. Budell, Thomas P. Camino, Todd W. Davies, Ross W. Keesler, Steven G. Rosser, David B. Stone
  • Patent number: 7351917
    Abstract: A method, structure, and method of design relating an electrical structure that includes a metal voltage plane laminated to a dielectric substrate. A determination is made as to where to place an opening for venting gases generated during fabrication of the dielectric laminate. An identification is made of a problematic opening in the metal voltage plane that is above or below a corresponding metal signal line within the dielectric laminate, such that an image of a portion of the corresponding metal signal line projects across the problematic opening. An electrically conductive strip is positioned across the problematic opening, such that the strip includes the image. In fabrication, the dielectric substrate having the metal signal line therein is provided. The metal voltage plane is laminated to the dielectric substrate. The opening in the metal voltage plane is formed such that the strip is across the opening and includes the image.
    Type: Grant
    Filed: October 17, 2005
    Date of Patent: April 1, 2008
    Assignee: International Business Machines Corporation
    Inventors: Timothy W. Budell, Thomas P. Comino, Todd W. Davies, Ross W. Keesler, Steven G. Rosser, David B. Stone
  • Patent number: 6977345
    Abstract: A method, structure, and method of design relating an electrical structure that includes a metal voltage plane laminated to a dielectric substrate. A determination is made as to where to place an opening for venting gases generated during fabrication of the dielectric laminate. An identification is made of a problematic opening in the metal voltage plane that is above or below a corresponding metal signal line within the dielectric laminate, such that an image of a portion of the corresponding metal signal line projects across the problematic opening. An electrically conductive strip is positioned across the problematic opening, such that the strip includes the image. In fabrication, the dielectric substrate having the metal signal line therein is provided. The metal voltage plane is laminated to the dielectric substrate. The opening in the metal voltage plane is formed such that the strip is across the opening and includes the image.
    Type: Grant
    Filed: January 8, 2002
    Date of Patent: December 20, 2005
    Assignee: International Business Machines Corporation
    Inventors: Timothy W. Budell, Thomas P. Comino, Todd W. Davies, Ross W. Keesler, Steven G. Rosser, David B. Stone
  • Publication number: 20030127249
    Abstract: A method, structure, and method of design relating an electrical structure that includes a metal voltage plane laminated to a dielectric substrate. A determination is made as to where to place an opening for venting gases generated during fabrication of the dielectric laminate. An identification is made of a problematic opening in the metal voltage plane that is above or below a corresponding metal signal line within the dielectric laminate, such that an image of a portion of the corresponding metal signal line projects across the problematic opening. An electrically conductive strip is positioned across the problematic opening, such that the strip includes the image. In fabrication, the dielectric substrate having the metal signal line therein is provided. The metal voltage plane is laminated to the dielectric substrate. The opening in the metal voltage plane is formed such that the strip is across the opening and includes the image.
    Type: Application
    Filed: January 8, 2002
    Publication date: July 10, 2003
    Applicant: International Business Machines Corporation
    Inventors: Timothy W. Budell, Thomas P. Comino, Todd W. Davies, Ross W. Keesler, Steven G. Rosser, David B. Stone
  • Patent number: 6538213
    Abstract: An organic integrated circuit chip carrier for high density integrated circuit chip attach, wherein the contact pads or microvias which provide electrical interconnections to external circuitry are located in a first array pattern, while the plated through holes or through-vias are located in a second array pattern. This allows utilization of wiring channels within the chip carrier in which signal wiring traces can be routed.
    Type: Grant
    Filed: February 18, 2000
    Date of Patent: March 25, 2003
    Assignee: International Business Machines Corporation
    Inventors: Timothy F. Carden, Todd W. Davies, Ross W. Keesler, Robert D. Sebesta, David B. Stone, Cheryl L. Tytran-Palomaki