Abstract: A restart controller for an information handling system includes a first latch and a second latch. An output of the second latch is coupled to an input of the first latch. The restart controller is configured to detect that the information handling system has been shut down responsive to a first disorderly shutdown, and in response to detecting the shut down, to set the first latch, initiate a first startup of the information handling system to enable a remote wake mechanism of a chipset of the information handling system, and determine, at the second latch, that a basic input/output system (BIOS) of the information handling system is operational. In response to determining that the BIOS is operational, The restart controller is further configured to initiate an orderly shutdown of the information handling system, and clear the first latch.

Abstract: Disclosed are techniques for recovering system configuration settings, such as remote management, of an information handling system following a disorderly shutdown. A restart controller detects a disorderly shutdown of an information handling system and, in response, sets a disorderly shutdown flag and restarts the information handling system. During the restart, the basic input/output system (BIOS) checks the disorderly shutdown flag as part of its power-on housekeeping. In response to determining the disorderly shutdown flag has been set, the BIOS reconfigures the system configuration settings, such as the power management scheme, of the information handling system so as to enable one or more remote wake mechanisms, such as wake-on-LAN or wake-on-ring. The BIOS then performs an orderly shutdown of the information handling system to place the information handling system in a low-power state, from which the information handling system can be awoken via the remote wake mechanism.

Abstract: Disclosed are techniques for recovering system configuration settings, such as remote management, of an information handling system following a disorderly shutdown. A restart controller detects a disorderly shutdown of an information handling system and, in response, sets a disorderly shutdown flag and restarts the information handling system. During the restart, the basic input/output system (BIOS) checks the disorderly shutdown flag as part of its power-on housekeeping. In response to determining the disorderly shutdown flag has been set, the BIOS reconfigures the system configuration settings, such as the power management scheme, of the information handling system so as to enable one or more remote wake mechanisms, such as wake-on-LAN or wake-on-ring. The BIOS then performs an orderly shutdown of the information handling system to place the information handling system in a low-power state, from which the information handling system can be awoken via the remote wake mechanism.

Abstract: Plural information handling systems interface through a KVM switch with a DVI display with the KVM switch supporting selection of the information handling system providing display information to the display. A hotswap switch initiates a hotswap signal to the information handling system that is selected to provide display information to the display. Receipt of the hotswap signal at the information handling system results in the driver of the selected information handling system redetecting the display with a communication through the DDC channel and transfer of EDID information from the display to the selected information handling system so that the selected information handling system drives a desired display port, such as by sending display information through a TDMS channel instead of default VGA channel.

Abstract: Bus numbering management for an information handling system, such as a personal computer, is provided by interfacing one or more selectively hidden devices with one or more buses through either a hardware or software implementation. If an inactive bus becomes active, then disabling of a selectively hidden device interfaced with another active bus provides a bus number to the newly active bus. For instance, if a graphics capability is added to a computer system through a PCI bus, a PCI bridge associated with a second PCI bus is disabled so that the PCI bus number for the portion of the second PCI bus between the chipset of the computer system and the PCI bridge is available for use as the PCI bus number for the PCI bus associated with the graphics capability. The PCI bus number for the portion of the second PCI bus between the PCI bridge and existing peripheral devices is available for use for both portions of the second PCI bus.

Abstract: An energy discharge resistance is isolated from storage capacitance containing a voltage charge until power is removed from the storage capacitance. Then the discharge resistance may be coupled to the storage capacitance to drain residual charge therefrom. The discharge resistance is coupled to the storage capacitance when external power is removed and is un-coupled from the storage capacitance when external power is applied to the storage capacitance. In this way, unnecessary power draw during operation or standby of an electronic system is substantially eliminated.

Abstract: Bus numbering management for an information handling system, such as a personal computer, is provided by interfacing one or more selectively hidden devices with one or more buses through either a hardware or software implementation. If an inactive bus becomes active, then disabling of a selectively hidden device interfaced with another active bus provides a bus number to the newly active bus. For instance, if a graphics capability is added to a computer system through a PCI bus, a PCI bridge associated with a second PCI bus is disabled so that the PCI bus number for the portion of the second PCI bus between the chipset of the computer system and the PCI bridge is available for use as the PCI bus number for the PCI bus associated with the graphics capability. The PCI bus number for the portion of the second PCI bus between the PCI bridge and existing peripheral devices is available for use for both portions of the second PCI bus.

Abstract: An energy discharge resistance is isolated from storage capacitance containing a voltage charge until power is removed from the storage capacitance. Then the discharge resistance may be coupled to the storage capacitance to drain residual charge therefrom. The discharge resistance is coupled to the storage capacitance when external power is removed and is un-coupled from the storage capacitance when external power is applied to the storage capacitance. In this way, unnecessary power draw during operation or standby of an electronic system is substantially eliminated.

Abstract: Bus numbering management for an information handling system, such as a personal computer, is provided by interfacing one or more selectively hidden devices with one or more buses through either a hardware or software implementation. If an inactive bus becomes active, then disabling of a selectively hidden device interfaced with another active bus provides a bus number to the newly active bus. For instance, if a graphics capability is added to a computer system through a PCI bus, a PCI bridge associated with a second PCI bus is disabled so that the PCI bus number for the portion of the second PCI bus between the chipset of the computer system and the PCI bridge is available for use as the PCI bus number for the PCI bus associated with the graphics capability. The PCI bus number for the portion of the second PCI bus between the PCI bridge and existing peripheral devices is available for use for both portions of the second PCI bus.