Abstract: In a high speed digital communication receiver, an n-stage oscillator of frequency f has a plurality of n stages with n variable analog delays connected to respective ones of the n stages, outputs of the n variable analog delays providing n successive cycles of a clock signal of frequency n×f. A delay control circuit varies the delay interposed by each of the variable delays through a range of 1/(n×f). The delay control circuit can vary the delay in m equal steps, whereby the oscillator exhibits n×m virtual oscillator stages, so that the oscillator provides a phase resolution of 1/(m×n×f).