Abstract: Disclosed herein are assemblies for optical communication in quantum computing. For example, in some embodiments, a quantum computing assembly may include control circuitry having an optical interface to external electronic circuitry.

Abstract: Quantum circuit assemblies that employ active pulse shaping in order to be able to control states of a plurality of qubits with signal pulses propagated over a shared signal propagation channel are disclosed. An example quantum circuit assembly includes a quantum circuit component that includes a first qubit, associated with a first frequency to control the state of the first qubit, and a second qubit, associated with a second frequency to control the state of the second qubit. A shared transmission channel is coupled to the first and second qubits. The assembly further includes a signal pulse generation circuit, configured to generate a signal pulse to be propagated over the shared transmission channel to control the state of the first qubit, where the signal pulse has a center frequency at the first frequency, a bandwidth that includes the second frequency, and a notch at the second frequency.

Abstract: Systems and methods for synchronizing operation of control circuits in quantum circuit assemblies are disclosed. An example assembly for controlling operation of a qubit device includes a plurality of control circuits and an event synchronization arrangement. The plurality of control circuits may include a first and a second control circuits, configured to perform, respectively, first and second actions to control operation of the qubit device. The event synchronization arrangement may be used to control operation of the plurality of control circuits to provide to the second control circuit an indication that the first control circuit performed the first action, and to configure the second control circuit to perform the second action in response to receiving the indication that the first control circuit performed the first action. Assemblies disclosed herein provide improved control over qubits, good scalability in the number of qubits included in the device, and/or design flexibility.

Abstract: An apparatus is provided which comprises: a plurality of data routers to route data packets, wherein the plurality of data routers comprises: a first data router comprising a trace port, and a second data router coupled to a component; and one or more trace routers to route trace information of the apparatus, wherein a first trace router of the one or more trace routers is coupled to the trace port, and wherein the first trace router is to route configuration information from the component to the trace port, the configuration information to configure the trace port.

Abstract: Embodiments of the present disclosure may relate to an apparatus with a first component and a second component coupled with the first component by a plurality of signal wires. A first wire of the plurality of signal wires may be to carry a command byte of a packet and a first data byte of the packet from the first component to the second component. A second wire of the plurality of signal wires may be to carry a second data byte of the packet from the first component to the second component when the first signal wire carries the command byte of the packet and carry a third data byte of the packet from the first component to the second component when the first signal wire carries the first data byte of the packet. Other embodiments may be described or claimed.

Abstract: An apparatus is provided which comprises: a plurality of data routers to route data packets, wherein the plurality of data routers comprises: a first data router comprising a trace port, and a second data router coupled to a component; and one or more trace routers to route trace information of the apparatus, wherein a first trace router of the one or more trace routers is coupled to the trace port, and wherein the first trace router is to route configuration information from the component to the trace port, the configuration information to configure the trace port.

Abstract: Embodiments of the present disclosure may relate to an apparatus with a first component and a second component coupled with the first component by a plurality of signal wires. A first wire of the plurality of signal wires may be to carry a command byte of a packet and a first data byte of the packet from the first component to the second component. A second wire of the plurality of signal wires may be to carry a second data byte of the packet from the first component to the second component when the first signal wire carries the command byte of the packet and carry a third data byte of the packet from the first component to the second component when the first signal wire carries the first data byte of the packet. Other embodiments may be described or claimed.

Abstract: A network interface is provided which comprises: a first buffer configured to buffer a first flow of a first type of commands from a first device to a second device, wherein the first device is configured in accordance with a first bus interconnect protocol and the second device is configured in accordance with a second bus interconnect protocol; a second buffer configured to buffer a second flow of a second type of commands from the first device to the second device; and an arbiter configured to arbitrate between the first flow and the second flow, and selectively output one or more commands of the first type and one or more commands of the second type.